參數(shù)資料
型號(hào)： XE8801AMI027LF
廠商： Semtech
文件頁數(shù)： 33/135頁
文件大小： 0K
描述： IC DAS 16BIT FLASH 8K MTP 44LQFP
標(biāo)準(zhǔn)包裝： 800
系列： XE880x
應(yīng)用： 感測機(jī)
核心處理器： Coolrisc816?
程序存儲(chǔ)器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 托盤
供應(yīng)商設(shè)備封裝： 44-MLPQ（7x7）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2005
www.semtech.com
18-10
XE8801A – SX8801R
When the capture function is active, the A and B counters must be written with the value 0xFF and can either
upcount or downcount. They do count circularly: they restart at zero or at the maximal value (either 0xFF when not
cascaded or 0xFFFF when cascaded) when respectively an overflow or an underflow condition occurs in the
counting.
CapFunc(1:0) in register RegCntConfig2 determines if the capture function is enabled or not and selects which
edges of the capture signal source are valid for the capture operation. The source of the capture signal can be
selected by setting CapSel(1:0) in the RegCntConfig2 register. For all sources, rising, falling or both edge
sensitivity can be selected. Table 18-14 shows the capture condition as a function of the setting of these
configuration bits.
CapSel(1:0)
Selected capture signal
CapFunc
Selected condition
Capture condition
11
1 K
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
1 K rising edge
1 K falling edge
1 K both edges
10
32 K
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
32 K rising edge
32 K falling edge
32 K both edges
01
PA3
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
PA3 rising edge
PA3 falling edge
PA3 both edges
00
PA2
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
PA2 rising edge
PA2 falling edge
PA2 both edges
Table 18-14: Capture condition selection
CapFunc(1:0) and CapSel(1:0) can be modified only when the counters are stopped otherwise data may be
corrupted during one counter clock cycle.
Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the
capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the
effective capture condition occurred. When the counters A and B are not cascaded and do not operate on the
same clock, the interruptions on IrqA and IrqB which inform that the capture condition was met, may appear at
different moments. In this case, the processor should read the shadow register associated to a counter only if the
interruption related to this counter has been detected.
It must be noted that when counters A and B are cascaded, the capture might happen at different cycles for the A
and B registers. This is due to the asynchronous relationship between counter and capture clock and to the fact
that the capture condition detection is independent for A and B counters.
Not
Recommended
for
New
Designs
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