參數資料
型號: XE8801AMI027LF
廠商: Semtech
文件頁數: 111/135頁
文件大小: 0K
描述: IC DAS 16BIT FLASH 8K MTP 44LQFP
標準包裝: 800
系列: XE880x
應用: 感測機
核心處理器: Coolrisc816?
程序存儲器類型: 閃存(22 kB)
控制器系列: XE8000
RAM 容量: 512 x 8
接口: UART,USRT
輸入/輸出數: 24
電源電壓: 2.4 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 托盤
供應商設備封裝: 44-MLPQ(7x7)
產品目錄頁面: 585 (CN2011-ZH PDF)
配用: XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2005
www.semtech.com
14-5
XE8801A – SX8801R
The bits UartEnRx1 and UartEnRx2 are used to enable or disable the reception. When one is set to 1, the
reception is enabled.
The word length (7 or 8 data bits) can be chosen with UartWL. A parity bit is added during transmission or checked
during reception if UartPE is set. The parity mode (odd or even) can be chosen with UartPM.
Setting the bits UartXRx and UartXTx inverts the Rx respectively Tx signals.
The bit UartEcho is used to send the received data automatically back. The transmission function becomes then:
Tx = Rx XOR UartXTx.
14.6.2
Transmission
In order to send data, the transmitter has to be enabled by setting the bit UartEnTx. Data to be sent has to be
written to the register RegUartTx. The bit UartTxFull in RegUartTxSta then goes to 1, indicating to the transmitter
that a new word is available. As soon as the transmitter has finished sending the previous word, it then loads the
contents of the register RegUartTx to an internal shift register and clears the UartTxFull bit. An interrupt is
generated on Irq_uart_Tx at the falling edge of the UartTxFull bit. The bit UartTxBusy in RegUartTxSta shows
that the transmitter is busy transmitting a word.
A timing diagram is shown in Figure 14-1. Data are sent LSB first.
New data should be written to the register RegUartTx only while UartTxFull is 0, otherwise data will be lost.
Asynchronous Transmission
write to RegUartTx
RegUartTx
word 1
reguarttx_shift
word 1
shift clock
Tx
start
b0
b1
b6/7
parity
stop
UartTxBusy
UartTxFull
Irq_uart_Tx
Asynchronous Transmission (back to back)
word 1
word 2
write to RegUartTx
RegUartTx
word 1
word 2
reguarttx_shift
word 1
word 2
shift clock
Tx
start
b0
b6/7
stop
start
UartTxBusy
UartTxFull
Irq_uart_Tx
Figure 14-1. Uart transmission timing diagram.
Not
Recommended
for
New
Designs
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