參數(shù)資料
型號: XCV405E-6FG676C
廠商: Xilinx Inc
文件頁數(shù): 91/118頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V C-TEMP 676-FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計: 573440
輸入/輸出數(shù): 404
門數(shù): 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 676-BGA
供應商設備封裝: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4
DS025-3 (v3.0) March 21, 2014
18
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those
parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the
recommended operating conditions.
Description
Symbol
F
CLKIN
Speed Grade
Units
-8
-7
-6
Min
Max
Min
Max
Min
Max
Input Clock Frequency (CLKDLLHF)
FCLKINHF
60
320
60
320
60
260
MHz
Input Clock Frequency (CLKDLL)
FCLKINLF
25
160
25
160
25
135
MHz
Input Clock Low/High Pulse Width
TDLLPW
≥25 MHz
5.0
ns
≥50 MHz
3.0
ns
≥100 MHz
2.4
ns
≥150 MHz
2.0
ns
≥200 MHz
1.8
ns
≥250 MHz
1.5
ns
≥300 MHz
1.3
NA
ns
Figure 4: DLL Timing Waveforms
TCLKIN
TCLKIN + TIPTOL
Period Tolerance: the allowed input clock period change in nanoseconds.
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
_
ds022_24_091200
Ideal Period
Actual Period
+
Jitter
+/- Jitter
+ Maximum
Phase Difference
Phase Offset and Maximum Phase Difference
+ Phase Offset
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相關代理商/技術參數(shù)
參數(shù)描述
XCV405E-6FG676I 功能描述:IC FPGA 1.8V 676-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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