參數(shù)資料
型號(hào)： XCV405E-6FG676C
廠(chǎng)商： Xilinx Inc
文件頁(yè)數(shù)： 32/118頁(yè)
文件大小： 0K
描述： IC FPGA 1.8V C-TEMP 676-FBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-E EM
LAB/CLB數(shù)： 2400
邏輯元件/單元數(shù)： 10800
RAM 位總計(jì)： 573440
輸入/輸出數(shù)： 404
門(mén)數(shù)： 129600
電源電壓： 1.71 V ~ 1.89 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
16
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
either asserted or de-asserted. Otherwise an abort is
initiated, as described below.
2.
Drive data onto D[7:0]. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.
3.
At the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance instead
occurs on the first clock after BUSY goes Low, and the
data must be held until this has happened.
4.
Repeat steps 2 and 3 until all the data has been sent.
5.
De-assert CS and WRITE.
A flowchart for the write operation appears in Figure 18.
Note that if CCLK is slower than fCCNH, the FPGA never
asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word boundar-
ies, and the FPGA requires a new synchronization word
prior to accepting any new packets.
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in Figure 19.
Table 11:
SelectMAP Write Timing Characteristics
Description
Symbol
Values
Units
CCLK
D0-7 Setup/Hold
1/2
TSMDCC/TSMCCD
5.0 / 1.7
ns, min
CS Setup/Hold
3/4
TSMCSCC/TSMCCCS
7.0 / 1.7
ns, min
WRITE Setup/Hold
5/6
TSMCCW/TSMWCC
7.0 / 1.7
ns, min
BUSY Propagation Delay
7
TSMCKBY
12.0
ns, max
Maximum Frequency
FCC
66
MHz, max
Maximum Frequency with no handshake
FCCNH
50
MHz, max
Figure 17: Write Operations
DS022_45_071702
CCLK
No Write
Write
No Write
Write
DATA[0:7]
CS
WRITE
3
5
BUSY
4
6
7
1
2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV405E-6FG676I 功能描述:IC FPGA 1.8V 676-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV405E-6FG900C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6FG900I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-7BG404C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-7BG404I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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