
Virtex-E 1.8 V Field Programmable Gate Arrays
R
Module 4 of 4
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Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Pinout Differences Between Virtex and Virtex-E Families
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
XCV200E Device, FG456 Package
The Virtex-E XCV200E has two I/O pins swapped with the
Virtex XCV200 to accommodate differential clock pairing.
XCV400E Device, FG676 Package
The Virtex-E XCV400E has two I/O pins swapped with the
Virtex XCV400 to accommodate differential clock pairing.
All Devices, PQ240 and HQ240 Packages
The Virtex devices in PQ240 and HQ240 packages do not
have VCCO banking, but Virtex-E devices do. To achieve
this, eight Virtex I/O pins (P232, P207, P176, P146, P116,
P85, P55, and P25) are now VCCO pins in the Virtex-E fam-
ily. This change also requires one Virtex I/O or VREF pin to
be swapped with a standard I/O pin.
Additionally, accommodating differential clock input pairs in
Virtex-E caused some IO_VREF differences in the XCV400E
and XCV600E devices only. Virtex IO_VREF pins P215 and
P87 are Virtex-E IO_VREF pins P216 and P86, respectively.
Virtex-E pins P215 and P87 are IO_DLL.
Table 1: Pinout Differences Summary
Part
Package
Pins
Virtex
Virtex-E
XCV200
FG456
E11, U11
I/O
No Connect
B11, AA11
No Connect
IO_LVDS_DLL
XCV400
FG676
D13, Y13
I/O
No Connect
B13, AF13
No Connect
IO_LVDS_DLL
XCV400/600
PQ240/HQ240
P215, P87
IO_VREF
IO_LVDS_DLL
P216, P86
I/O
IO_VREF
All
PQ240/HQ240
P232, P207, P176, P146, P116, P85, P55, and P25
I/O
VCCO
P231
I/O
IO_VREF