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參數(shù)資料
| 型號： | XCV200-6PQG240I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 167K |
| 代理商： | XCV200-6PQG240I |
Virtex 2.5 V Field Programmable Gate Arrays
R
DS003-3 (v3.2) September 10, 2002
Module 3 of 4
Production Product Specification
1-800-255-7778
17
Virtex Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Global Clock Input-to-Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Description
Symbol
Device
Speed Grade
Units
Min
-6
-5
-4
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, with DLL.
For data output with different standards, adjust
delays with the values shown in Output Delay
Adjustments.
TICKOFDLL
XCV50
1.0
3.1
3.3
3.6
ns, max
XCV100
1.0
3.1
3.3
3.6
ns, max
XCV150
1.0
3.1
3.3
3.6
ns, max
XCV200
1.0
3.1
3.3
3.6
ns, max
XCV300
1.0
3.1
3.3
3.6
ns, max
XCV400
1.0
3.1
3.3
3.6
ns, max
XCV600
1.0
3.1
3.3
3.6
ns, max
XCV800
1.0
3.1
3.3
3.6
ns, max
XCV1000
1.0
3.1
3.3
3.6
ns, max
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
3.
DLL output jitter is already included in the timing calculation.
Description
Symbol
Device
Speed Grade
Units
Min
-6
-5
-4
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without DLL.
For data output with different standards, adjust
delays with the values shown in Input and Output
Delay Adjustments.
For I/O standards requiring VREF, such as GTL,
GTL+, SSTL, HSTL, CTT, and AGO, an additional
600 ps must be added.
TICKOF
XCV50
1.5
4.6
5.1
5.7
ns, max
XCV100
1.5
4.6
5.1
5.7
ns, max
XCV150
1.5
4.7
5.2
5.8
ns, max
XCV200
1.5
4.7
5.2
5.8
ns, max
XCV300
1.5
4.7
5.2
5.9
ns, max
XCV400
1.5
4.8
5.3
6.0
ns, max
XCV600
1.6
4.9
5.4
6.0
ns, max
XCV800
1.6
4.9
5.5
6.2
ns, max
XCV1000
1.7
5.0
5.6
6.3
ns, max
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV200E | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
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| XCV200E-6BG352C | 功能描述:IC FPGA 1.8V C-TEMP 352-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV200E-6BG352C0773 | 制造商:Xilinx 功能描述: |
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