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參數(shù)資料
| 型號(hào)： | XCV200-6PQG240I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 167K |
| 代理商： | XCV200-6PQG240I |
Virtex 2.5 V Field Programmable Gate Arrays
R
Module 3 of 4
DS003-3 (v3.2) September 10, 2002
4
1-800-255-7778
Production Product Specification
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
power supply voltage of the device(1) from 0 V. The current is highest at the fastest suggested ramp rate (0 V to nominal
voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 V to nominal voltage in 50 ms). For more details on power
supply requirements, see Application Note XAPP158 on www.xilinx.com.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed output currents over the
recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen
to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO for each standard
with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
Product
Description(2)
Current Requirement(1,3)
Virtex Family, Commercial Grade
Minimum required current supply
500 mA
Virtex Family, Industrial Grade
Minimum required current supply
2 A
Notes:
1.
Ramp rate used for this specification is from 0 - 2.7 VDC. Peak current occurs on or near the internal power-on reset threshold of
1.0V and lasts for less than 3 ms.
2.
Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
3.
Larger currents can result if ramp rates are forced to be faster.
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, min
V, max
V, min
V, max
V, Max
V, Min
mA
LVTTL(1)
– 0.5
0.8
2.0
5.5
0.4
2.4
24
–24
LVCMOS2
– 0.5
.7
1.7
5.5
0.4
1.9
12
–12
PCI, 3.3 V
– 0.5
44% VCCINT
60% VCCINT
VCCO + 0.5
10% VCCO
90% VCCO
Note 2
PCI, 5.0 V
– 0.5
0.8
2.0
5.5
0.55
2.4
Note 2
GTL
– 0.5
VREF – 0.05
VREF + 0.05
3.6
0.4
n/a
40
n/a
GTL+
– 0.5
VREF – 0.1
VREF + 0.1
3.6
0.6
n/a
36
n/a
HSTL I(3)
– 0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
8
–8
HSTL III
– 0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
24
–8
HSTL IV
– 0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
48
–8
SSTL3 I
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.6
VREF + 0.6
8
–8
SSTL3 II
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
16
–16
SSTL2 I
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.61 VREF + 0.61
7.6
–7.6
SSTL2 II
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.80 VREF + 0.80
15.2
–15.2
CTT
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.4
VREF + 0.4
8
–8
AGP
– 0.5
VREF – 0.2
VREF + 0.2
3.6
10% VCCO
90% VCCO
Note 2
Notes:
1.
VOL and VOH for lower drive currents are sample tested.
2.
Tested according to the relevant specifications.
3.
DC input and output levels for HSTL18 (HSTL I/O standard with VCCO of 1.8 V) are provided in an HSTL white paper on
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