參數(shù)資料
型號(hào)： XCS30-4VQ100C
廠商： Xilinx Inc
文件頁數(shù)： 51/83頁
文件大?。?/td> 0K
描述： IC FPGA 5V C-TEMP 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®
LAB/CLB數(shù)： 576
邏輯元件/單元數(shù)： 1368
RAM 位總計(jì)： 18432
輸入/輸出數(shù)： 77
門數(shù)： 30000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
55
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan-XL Family CLB Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and expressed in nanoseconds unless otherwise noted.
Symbol
Description
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Clocks
TCH
Clock High time
2.0
-
2.3
-
ns
TCL
Clock Low time
2.0
-
2.3
-
ns
Combinatorial Delays
TILO
F/G inputs to X/Y outputs
-
1.0
-
1.1
ns
TIHO
F/G inputs via H to X/Y outputs
-
1.7
-
2.0
ns
TITO
F/G inputs via transparent latch to Q outputs
-
1.5
-
1.8
ns
THH1O
C inputs via H1 via H to X/Y outputs
-
1.5
-
1.8
ns
Sequential Delays
TCKO
Clock K to Flip-Flop or latch outputs Q
-
1.2
-
1.4
ns
Setup Time before Clock K
TICK
F/G inputs
0.6
-
0.7
-
ns
TIHCK
F/G inputs via H
1.3
-
1.6
-
ns
Hold Time after Clock K
All Hold times, all devices
0.0
-
0.0
-
ns
Set/Reset Direct
TRPW
Width (High)
2.5
-
2.8
-
ns
TRIO
Delay from C inputs via S/R, going High to Q
-
2.3
-
2.7
ns
Global Set/Reset
TMRW
Minimum GSR Pulse Width
10.5
-
11.5
-
ns
TMRQ
Delay from GSR input to any Q
See page 60 for TRRI values per device.
FTOG
Toggle Frequency (MHz)
(for export control purposes)
-
250
-
217
MHz
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