參數(shù)資料
型號(hào)： XCS30-3BG256C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 49/83頁(yè)
文件大小： 0K
描述： IC FPGA 5V C-TEMP 256-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： Spartan®
LAB/CLB數(shù)： 576
邏輯元件/單元數(shù)： 1368
RAM 位總計(jì)： 18432
輸入/輸出數(shù)： 192
門數(shù)： 30000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BBGA
供應(yīng)商設(shè)備封裝： 256-PBGA
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
53
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan-XL Family DC Characteristics Over Operating Conditions
Supply Current Requirements During Power-On
Spartan-XL FPGAs require that a minimum supply current
ICCPO be provided to the VCC lines for a successful power
on. If more current is available, the FPGA can consume
more than ICCPO min., though this cannot adversely affect
reliability.
A maximum limit for ICCPO is not specified. Be careful when
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of ICCPO by limiting the supply current
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
Symbol
Description
Min
Typ.
Max
Units
VOH
High-level output voltage @ IOH = –4.0 mA, VCC min (LVTTL)
2.4
-
V
High-level output voltage @ IOH = –500 μA, (LVCMOS)
90% VCC
--
V
VOL
Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL)(1)
--
0.4
V
Low-level output voltage @ IOL = 24.0 mA, VCC min (LVTTL)(2)
--
0.4
V
Low-level output voltage @ IOL = 1500 μA, (LVCMOS)
-
10% VCC
V
VDR
Data retention supply voltage (below which configuration data
may be lost)
2.5
-
V
ICCO
Quiescent FPGA supply current(3,4)
Commercial
-
0.1
2.5
mA
Industrial
-
0.1
5
mA
ICCPD
Power Down FPGA supply current(3,5)
Commercial
-
0.1
2.5
mA
Industrial
-
0.1
5
mA
IL
Input or output leakage current
–10
-
10
μA
CIN
Input capacitance (sample tested)
-
10
pF
IRPU
Pad pull-up (when selected) @ VIN = 0V (sample tested)
0.02
-
0.25
mA
IRPD
Pad pull-down (when selected) @ VIN = 3.3V (sample tested)
0.02
-
mA
Notes:
1.
With up to 64 pins simultaneously sinking 12 mA (default mode).
2.
With up to 64 pins simultaneously sinking 24 mA (with 24 mA option selected).
3.
With 5V tolerance not selected, no internal oscillators, and the FPGA configured with the Tie option.
4.
With no output current loads, no active input resistors, and all package pins at VCC or GND.
5.
With PWRDWN active.
Symbol
Description
Min
Max
Units
ICCPO
Total VCC supply current required during power-on
100
-
mA
TCCPO
VCC ramp time(2,3)
-50
ms
Notes:
1.
The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCC ramps from 0 to 3.3V.
2.
The ramp time is measured from GND to VCC max on a fully loaded board.
3.
VCC must not dip in the negative direction during power on.
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