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參數(shù)資料
| 型號： | XCS30-3BG256C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 17/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 5V C-TEMP 256-PBGA |
| 標準包裝： | 40 |
| 系列： | Spartan® |
| LAB/CLB數(shù)： | 576 |
| 邏輯元件/單元數(shù)： | 1368 |
| RAM 位總計： | 18432 |
| 輸入/輸出數(shù)： | 192 |
| 門數(shù)： | 30000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-BBGA |
| 供應商設備封裝： | 256-PBGA |
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Spartan and Spartan-XL FPGA Families Data Sheet
24
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Even if the boundary scan symbol is used in a design, the
input pins TMS, TCK, and TDI can still be used as inputs to
be routed to internal logic. Care must be taken not to force
the chip into an undesired boundary scan state by inadver-
tently applying boundary scan input patterns to these pins.
The simplest way to prevent this is to keep TMS High, and
then apply whatever signal is desired to TDI and TCK.
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant during
configuration. In some applications, a situation may occur
where TMS or TCK is driven during configuration. This may
cause the device to go into boundary scan mode and dis-
rupt the configuration process.
To prevent activation of boundary scan during configuration,
do either of the following:
TMS: Tie High to put the Test Access Port controller
in a benign RESET state.
TCK: Tie High or Low—do not toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note, "Boundary Scan in FPGA Devices. "
Boundary Scan Enhancements (Spartan-XL Family
Only)
Spartan-XL devices have improved boundary scan func-
tionality and performance in the following areas:
IDCODE: The IDCODE register is supported. By using the
IDCODE, the device connected to the JTAG port can be
determined. The use of the IDCODE enables selective con-
figuration dependent on the FPGA found.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
c = the company code (49h for Xilinx)
a = the array dimension in CLBs (ranges from 0Ah for
XCS05XL to 1Ch for XCS40XL)
f = the family code (02h for Spartan-XL family)
v = the die version number
Configuration State: The configuration state is available to
JTAG controllers.
Configuration Disable: The JTAG port can be prevented
from configuring the FPGA.
TCK Startup: TCK can now be used to clock the start-up
block in addition to other user clocks.
CCLK Holdoff: Changed the requirement for Boundary
Scan Configure or EXTEST to be issued prior to the release
of INIT pin and CCLK cycling.
Reissue Configure: The Boundary Scan Configure can be
reissued to recover from an unfinished attempt to configure
the device.
Bypass FF: Bypass FF and IOB is modified to provide
DRCLOCK only during BYPASS for the bypass flip-flop, and
during EXTEST or SAMPLE/PRELOAD for the IOB register.
Power-Down (Spartan-XL Family Only)
All Spartan/XL devices use a combination of efficient seg-
mented routing and advanced process technology to pro-
vide low power consumption under all conditions. The 3.3V
Spartan-XL family adds a dedicated active Low power-down
pin (PWRDWN) to reduce supply current to 100
μA typical.
The PWRDWN pin takes advantage of one of the unused
No Connect locations on the 5V Spartan device. The user
must de-select the "5V Tolerant I/Os" option in the Configu-
ration Options to achieve the specified Power Down current.
The PWRDWN pin has a default internal pull-up resistor,
allowing it to be left unconnected if unused.
VCC must continue to be supplied during Power-down, and
configuration data is maintained. When the PWRDWN pin is
pulled Low, the input and output buffers are disabled. The
inputs are internally forced to a logic Low level, including the
MODE pins, DONE, CCLK, and TDO, and all internal
pull-up resistors are turned off. The PROGRAM pin is not
affected by Power Down. The GSR net is asserted during
Power Down, initializing all the flip-flops to their start-up
state.
PWRDWN has a minimum pulse width of 50 ns (Figure 23).
On entering the Power-down state, the inputs will be dis-
abled and the flip-flops set/reset, and then the outputs are
disabled about 10 ns later. The user may prefer to assert the
GTS or GSR signals before PWRDWN to affect the order of
events. When the PWRDWN signal is returned High, the
inputs will be enabled first, followed immediately by the
release of the GSR signal initializing the flip-flops. About 10
ns later, the outputs will be enabled. Allow 50 ns after the
release of PWRDWN before using the device.
Table 13: IDCODEs Assigned to Spartan-XL FPGAs
FPGA
IDCODE
XCS05XL
0040A093h
XCS10XL
0040E093h
XCS20XL
00414093h
XCS30XL
00418093h
XCS40XL
0041C093h
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