參數(shù)資料
型號： XCS05XL-4VQ144C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù)： 43/82頁
文件大?。?/td> 623K
代理商： XCS05XL-4VQ144C
Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
43
R
Spartan DC Characteristics Over Operating Conditions
Spartan Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Symbol
V
OH
Description
Min
2.4
Max
-
-
0.4
0.4
-
3.0
6.0
+10
10
0.25
-
Units
V
V
V
V
V
mA
mA
μ
A
pF
mA
mA
High-level output voltage @ I
OH
=
–
4.0 mA, V
CC
min
High-level output voltage @ I
OH
=
–
1.0 mA, V
CC
min
Low-level output voltage @ I
OL
= 12.0 mA, V
CC
min
(1)
TTL outputs
CMOS outputs
TTL outputs
CMOS outputs
V
CC
–
0.5
-
-
3.0
-
-
–
10
-
0.02
0.02
V
OL
V
DR
I
CCO
Data retention supply voltage (below which configuration data may be lost)
Quiescent FPGA supply current
(2)
Commercial
Industrial
I
L
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ V
IN
= 0V (sample tested)
Pad pull-down (when selected) @ V
IN
= 5V (sample tested)
C
IN
I
RPU
I
RPD
Notes:
1.
2.
With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
With no output current loads, no active input pull-up resistors, all package pins at V
CC
or GND, and the FPGA configured with a Tie
option.
Symbol
T
PG
Description
Device
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
Speed Grade
-4
Max
2.0
2.4
2.8
3.2
3.5
2.5
2.9
3.3
3.6
3.9
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-3
Max
4.0
4.3
5.4
5.8
6.4
4.4
4.7
5.8
6.2
6.7
From pad through Primary buffer, to any clock K
T
SG
From pad through Secondary buffer, to any clock K
相關(guān)PDF資料
PDF描述
XCS05XL-4VQ144I Spartan and Spartan-XL Families Field Programmable Gate Arrays
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCS05XL-4VQ144I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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XCS05XL-4VQ240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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