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| 型號： | XCS05XL-4VQ144C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 13/82頁 |
| 文件大?。?/td> | 623K |
| 代理商： | XCS05XL-4VQ144C |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
13
R
The four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs. The eight Global Low-Skew
buffers in the Spartan-XL devices combine short delay, neg-
ligible skew, and flexibility.
The Primary Global buffers must be driven by the semi-ded-
icated pads (PGCK1-4). The Secondary Global buffers can
be sourced by either semi-dedicated pads (SGCK1-4) or
internal nets. Each corner of the device has one Primary
buffer and one Secondary buffer. The Spartan-XL family
has eight global low-skew buffers, two in each corner. All
can be sourced by either semi-dedicated pads (GCK1-8) or
internal nets.
Using the library symbol called BUFG results in the software
choosing the appropriate clock buffer, based on the timing
requirements of the design. A global buffer should be spec-
ified for all timing-sensitive global signal distribution. To use
a global buffer, place a BUFGP (primary buffer), BUFGS
(secondary buffer), BUFGLS (Spartan-XL global low-skew
buffer), or BUFG (any buffer type) element in a schematic or
in HDL code.
Advanced Features Description
Distributed RAM
Optional modes for each CLB allow the function generators
(F-LUT and G-LUT) to be used as Random Access Memory
(RAM).
Read and write operations are significantly faster for this
on-chip RAM than for off-chip implementations. This speed
advantage is due to the relatively short signal propagation
delays within the FPGA.
Memory Configuration Overview
There are two available memory configuration modes: sin-
gle-port RAM and dual-port RAM. For both these modes,
write operations are synchronous (edge-triggered), while
read operations are asynchronous. In the single-port mode,
a single CLB can be configured as either a 16 x 1, (16 x 1)
x 2, or 32 x 1 RAM array. In the dual-port mode, a single
CLB can be configured only as one 16 x 1 RAM array. The
different CLB memory configurations are summarized in
Table 8
. Any of these possibilities can be individually pro-
grammed into a Spartan/XL CLB.
Figure 11:
5V Spartan Family Global Net Distribution
X4
X4
ds060_11_080400
X4
4
One BUFGP
per Global Line
One BUFGP
per Global Line
Any BUFGS
Any BUFGS
BUFGP
PGCK4
SGCK4
PGCK3
SGCK3
BUFGS
BUFGP
BUFGS
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
BUFGS
BUFGS
BUFGP
BUFGP
SGCK1
PGCK1
SGCK2
PGCK2
IOB
X4
locals
locals
locals
locals
l
l
l
l
l
l
l
l
4
4
4
CLB
CLB
locals
locals
CLB
CLB
locals
locals
Table 8:
CLB Memory Configurations
Mode
16 x 1
(16 x 1) x 2
32 x 1
Single-Port
√
√
√
Dual-Port
√
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相關(guān)代理商/技術(shù)參數(shù) |
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| XCS05XL-4VQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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| XCS05XL-4VQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-4VQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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