參數(shù)資料
型號(hào)： XCS05XL-4VQ144C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門(mén)陣列
文件頁(yè)數(shù)： 28/82頁(yè)
文件大?。?/td> 623K
代理商： XCS05XL-4VQ144C
Spartan and Spartan-XL Families Field Programmable Gate Arrays
28
www.xilinx.com
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
R
Slave Serial is the default mode if the Mode pins are left
unconnected, as they have weak pull-up resistors during
configuration.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
Serial Daisy Chain
Multiple devices with different configurations can be con-
nected together in a "daisy chain," and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins of
all devices in parallel, as shown in
Figure 25
. Connect the
DOUT of each device to the DIN of the next. The lead or
master FPGA and following slaves each passes resynchro-
nized configuration data coming from a single source. The
header data, including the length count, is passed through
and is captured by each FPGA when it recognizes the 0010
preamble. Following the length-count data, each FPGA out-
puts a High on DOUT until it has received its required num-
ber of data frames.
After an FPGA has received its configuration data, it passes
on any additional frame start bits and configuration data on
DOUT. When the total number of configuration clocks
applied after memory initialization equals the value of the
24-bit length count, the FPGAs begin the start-up sequence
and become operational together. FPGA I/O are normally
released two CCLK cycles after the last configuration bit is
received.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM File Formatter must
be used to combine the bitstreams for a daisy-chained con-
figuration.
Figure 25:
Master/Slave Serial Mode Circuit Diagram
Spartan
Master
Seria
l
Spartan
Slave
FPGA
Slave
Xilinx SPROM
PROGRAM
Note:
M2, M1, M0 can be shorted
to V
CC
if not used as I/O
MODE
DOUT
CCLK
DIN
LDC
INIT
CLK
DATA
V
CC
V
CC
+5V
CE
RESET/OE
CEO
V
PP
DONE
INIT
DONE
PROGRAM
PROGRAM
D/P
INIT
RESET
CCLK
DIN
CCLK
DIN
DOUT
DOUT
MODE
M1
M0
M2
(Low Reset Option Used)
3.3K
3.3K
3.3K
3.3K
DS060_25_061301
N/C
相關(guān)PDF資料
PDF描述
XCS05XL-4VQ144I Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ208C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ208I Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ240C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ240I Spartan and Spartan-XL Families Field Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCS05XL-4VQ144I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ208C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ208I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-4VQ240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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