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| 型號： | XCS05-3BG144C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 43/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05-3BG144C |
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R
DS060 (v1.5) March 2, 2000
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4-43
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless
otherwise noted.
Note 1: Delay adder for CMOS Outputs option (with fast slew rate option): for -3 speed grade, add 1.0 ns; for -4 speed grade, add 0.8 ns.
Note 2: Delay adder for CMOS Outputs option (with slow slew rate option): for -3 speed grade, add 2.0 ns; for -4 speed grade, add 1.5 ns.
Note 3: Output timing is measured at ~50% V
threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited
output rise/fall times are approximately two times longer than fast output rise/fall times.
Note 4: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Speed Grade
-4
-3
Units
Description
Symbol
Device
Min
Max
Min
Max
Clocks
Clock High
Clock Low
T
CH
T
CL
All devices
All devices
3.0
3.0
4.0
4.0
ns
ns
Propagation Delays - TTL Outputs
(Notes 1, 2)
Clock (OK) to Pad, fast
Clock (OK to Pad, slew-rate limited
Output (O) to Pad, fast
Output (O) to Pad, slew-rate limited
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid, fast
3-state to Pad active and valid, slew-rate limited
T
OKPOF
T
OKPOS
T
OPF
T
OPS
T
TSHZ
T
TSONF
T
TSONS
All devices
All devices
All devices
All devices
All devices
All devices
All devices
3.3
6.9
3.6
7.2
3.0
6.0
9.6
4.5
7.0
4.8
7.3
3.8
7.3
9.8
ns
ns
ns
ns
ns
ns
ns
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
T
OOK
T
OKO
T
ECOK
T
OKEC
All devices
All devices
All devices
All devices
2.5
0.0
2.0
0.0
3.8
0.0
2.7
0.5
ns
ns
ns
ns
Global Set/Reset
Minimum GSR pulse width
T
MRW
T
RPO
All devices
11.5
13.5
ns
Delay from GSR input to any Pad
XCS05
XCS10
XCS20
XCS30
XCS40
12.0
12.5
13.0
13.5
14.0
15.0
15.7
16.2
16.9
17.5
ns
ns
ns
ns
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS05-3BG144I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG208C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG256C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG256I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG280C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05-3BG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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