DS060 (v1.5) March 2, 2000
Powered by ICminer.com Electronic-Library Service CopyRight 2003
4-1
Introduction
The Spartan series is the first high-volume production
FPGA solution to deliver all the key requirements for ASIC
replacement up to 40,000 gates. These requirements
include high performance, on-chip RAM, core solutions and
prices that, in high volume, approach and in many cases
are equivalent to mask programmed ASIC devices.
The Spartan series is the result of more than 14 years of
FPGA design experience and feedback from thousands of
customers. By streamlining the Spartan series feature set,
leveraging advanced hybrid process technologies and
focusing on total cost management, the Spartan series
delivers the key features required by ASIC and other high-
volume logic users while avoiding the initial cost, long
development cycles and inherent risk of conventional
ASICs. The Spartan and Spartan-XL families in the
Spartan series have ten members, as shown in
Table 1
.
Spartan and Spartan-XL Features
Note: The Spartan series devices described in this data
First ASIC replacement FPGA for high-volume
production with on-chip RAM
Advanced process technology
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCORE and LogiCORE
predefined solutions available
Unlimited reprogrammability
Low cost
System level features
-
Available in both 5V and 3.3V versions
-
On-chip SelectRAM
TM
memory
-
Fully PCI compliant
-
Low power segmented routing architecture
-
Full readback capability for program verification and
internal node observability
-
Dedicated high-speed carry logic
-
Internal 3-state bus capability
-
Eight global low-skew clock or signal networks
-
IEEE 1149.1-compatible Boundary Scan logic
Versatile I/O and packaging
-
Low cost plastic packages available in all densities
-
Footprint compatibility in common packages
-
Individually programmable output slew-rate control
maximizes performance and reduces noise
-
Zero input register hold time simplifies system timing
Fully supported by powerful Xilinx development system
-
Foundation Series: Integrated, shrink-wrap software
-
Alliance Series: Dozens of PC and workstation third
party development systems supported
-
Fully automatic mapping, placement and routing
Additional Spartan-XL Features
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional mux or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compatible
Enhanced Boundary Scan
Express Mode configuration
Chip scale packaging
0
Spartan and Spartan-XL Families
Field Programmable Gate Arrays
DS060 (v1.5) March 2, 2000
0
0
Product Specification
R
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
Device
Logic
Cells
238
466
950
1368
1862
Max
System
Gates
5,000
10,000
20,000
30,000
40,000
Typical
Gate Range
(Logic and RAM)*
2,000 - 5,000
3,000 - 10,000
7,000 - 20,000
10,000 - 30,000
13,000 - 40,000
CLB
Matrix
10 x 10
14 x 14
20 x 20
24 x 24
28 x 28
Total
CLBs
100
196
400
576
784
Number
of
Flip-flops
360
616
1,120
1,536
2,016
Max.
Available
User I/O
77
112
160
192
224
XCS05 & XCS05XL
XCS10 & XCS10XL
XCS20 & XCS20XL
XCS30 & XCS30XL
XCS40 & XCS40XL
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.