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| 型號： | XCS05-3BG256C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 39/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05-3BG256C |
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R
DS060 (v1.5) March 2, 2000
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4-39
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan
devices and are expressed in nanoseconds unless otherwise noted.
Note 1: Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing.
Spartan CLB RAM Synchronous (Edge-Triggered) Write Timing
Dual Port RAM
Speed Grade
-4
-3
Units
Size
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
T
WCDS
T
WPDS
T
ASDS
T
AHDS
T
DSDS
T
DHDS
T
WSDS
T
WHDS
T
WODS
8.0
4.0
1.5
0.0
1.5
0.0
1.5
0.0
6.5
11.6
5.8
2.1
0.0
1.6
0.0
1.6
0.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCLK (K)
WE
ADDRESS
DATA IN
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSDS
T
WPDS
T
WHDS
X6474
DATA OUT
OLD
NEW
T
WODS
T
ILO
T
ILO
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
Single Port
Dual Port
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS05-3BG256I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG280C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG280I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG84C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG84I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05-3BG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS05-3BG280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG280I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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