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| 型號： | XCS05-3BG144C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 30/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05-3BG144C |
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R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-30
DS060 (v1.5) March 2, 2000
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Config-
uration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscil-
lator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configura-
tion frames and then tests the INIT input.
Initialization
During initialization and configuration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
The open drain INIT pin is released after the final initializa-
tion pass through the frame addresses. There is a deliber-
ate delay before a Master-mode device recognizes an
inactive INIT. Two internal clocks after the INIT pin is recog-
nized as High, the device samples the MODE pin to deter-
mine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.
Configuration
The 0010 preamble code indicates that the following 24 bits
represent the length count for serial modes. The length
count is the total number of configuration clocks needed to
load the complete configuration data. (Four additional con-
figuration clocks are required to complete the configuration
process, as discussed below.) After the preamble and the
length count have been passed through to any device in the
daisy chain, its DOUT is held High to prevent frame start
bits from reaching any daisy-chained devices. In Spar-
tan-XL Express mode, the length count bits are ignored,
and DOUT is held Low, to disable the next device in the
pseudo daisy chain.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configura-
tion clock is selected by the bitstream, the slower clock rate
is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configura-
tion frames have been loaded into an FPGA using a serial
mode, DOUT again follows the input data so that the
remaining data is passed on to the next device. In
Spartan-XL Express mode, when the first device is fully
programmed, DOUT goes High to enable the next device in
the chain.
INIT
High if
Master
Sample
Mode Line
Load One
Configuration
Data Frame
Frame
Error
ConPass
Data to DOUT
V
Valid
No
Yes
Yes
No
No
Yes
Operational
Start-Up
No
Yes
~1.3
μ
s per Frame
Master Delays Before
Sampling Mode Line
Goes Active
F
Pand Stop
s6076_01
EXTEST*
SAMPLE/PRELOAD
CBYPASS
(* if PROGRAM = High)
SAMPLE/PRELOAD
BYPASS
EXTEST
SAMPLE PRELOAD
USER 1
USER 2
CONFIGURE
READBACK
If Boundary Scan
is Selected
Config-
memory
Full
CoCCLK
Length
Count
Completely Clear
Configuration Memory
Once More
L
Boundary Scan
IAvailable:
I
ConKeep Clearing
One Time-Out Pulse
of 16 or 64 ms
P= Low
No
Yes
Yes
Figure 30: Power-up Configuration Sequence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05-3BG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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