參數資料
型號： XCS05-3BG144C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達和Spartan - xL的家庭現場可編程門陣列
文件頁數： 21/66頁
文件大小： 809K
代理商： XCS05-3BG144C
R
DS060 (v1.5) March 2, 2000
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4-21
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Boundary Scan Enhancements (Spartan-XL
only)
Spartan-XL devices have improved boundary scan func-
tionality and performance in the following areas:
IDCODE: The IDCODE register is supported. By using the
IDCODE, the device connected to the JTAG port can be
determined. The use of the IDCODE enables selective con-
figuration dependent on the FPGA found.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
c = the company code (49h for Xilinx)
a = the array dimension in CLBs (ranges from 0Ah for
XCS05XL to 1Ch for XCS40XL)
f = the family code (02h for Spartan-XL family)
v = the die version number (currently 0h)
Configuration State: The configuration state is available to
JTAG controllers.
Configuration Disable: The JTAG port can be prevented
from configuring the FPGA.
TCK Startup: TCK can now be used to clock the start-up
block in addition to other user clocks.
CCLK Holdoff: Changed the requirement for Boundary
Scan Configure or EXTEST to be issued prior to the
release of INIT pin and CCLK cycling.
Reissue Configure: The Boundary Scan Configure can be
reissued to recover from an unfinished attempt to configure
the device.
Bypass FF: Bypass FF and IOB is modified to provide
DRCLOCK only during BYPASS for the bypass flip-flop,
and during EXTEST or SAMPLE/PRELOAD for the IOB
register.
Power Down (Spartan-XL Only)
All Spartan/XL devices use a combination of efficient seg-
mented routing and advanced process technology to pro-
vide low power consumption under all conditions. The 3.3V
Spartan-XL family adds a dedicated active Low Power
Down pin (PWRDWN) to reduce supply current to 100
μ
A
typical. The PWRDWN pin takes advantage of one of the
unused No Connect locations on the 5V Spartan device.
The user must de-select the "5V Tolerant I/Os" option in the
Configuration Options to achieve the specified Power Down
current. The PWRDWN pin has a default internal pull-up
resistor, allowing it to be left unconnected if unused.
V
CC
must continue to be supplied during Power-down, and
configuration data is maintained. When the PWRDWN pin
is pulled Low, the input and output buffers are disabled. The
inputs are internally forced to a logic Low level, including
the MODE pins, DONE, CCLK, and TDO, and all internal
pull-up resistors are turned off. The PROGRAM pin is not
affected by Power Down. The GSR net is asserted during
Power Down, initializing all the flip-flops to their start-up
state.
PWRDWN has a minimum pulse width of 50 ns (
Figure 23
).
On entering the Power-down state, the inputs will be dis-
abled and the flip-flops set/reset, and then the outputs are
disabled about 10 ns later. The user may prefer to assert
the GTS or GSR signals before PWRDWN to affect the
order of events. When the PWRDWN signal is returned
High, the inputs will be enabled first, followed immediately
by the release of the GSR signal initializing the flip-flops.
About 10 ns later, the outputs will be enabled. Allow 50 ns
after the release of PWRDWN before using the device.
Power Down retains the configuration, but loses all data
stored in the device flip-flops. All inputs are interpreted as
Low, but the internal combinatorial logic is fully functional.
Make sure that the combination of all inputs Low and all
flip-flops set or reset in your design will not generate inter-
nal oscillations, or create permanent bus contention by acti-
vating internal bus drivers with conflicting data onto the
same long line.
During configuration, the PWRDWN pin must be High. If
the Power Down state is entered before or during configu-
ration, the device will restart configuration once the
PWRDWN signal is removed. Note that the configuration
pins are affected by Power Down and may not reflect their
normal function. If there is an external pull-up resistor on
the DONE pin, it will be High during Power Down even if the
device is not yet configured. Similarly, if PWRDWN is
asserted before configuration is completed, the INIT pin will
not indicate status information.
Table 13: IDCODEs Assigned to Spartan-XL FPGAs
FPGA
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
IDCODE
0040A093h
0040E093h
00414093h
00418093h
0041C093h
Power Down Mode
50ns
50ns
T
PWDW
Outputs
PWRDWN
Description
Power Down Time
Power Down Pulse Width
Symbol
TPWD
TPWDW
Min
50ns
50ns
Max
-
-
xap124_1
Figure 23: PWRDWN Pulse Timing
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相關代理商/技術參數
參數描述
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XCS05-3BG240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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