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| 型號(hào)： | XCS05-3BG144C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 20/66頁 |
| 文件大小： | 809K |
| 代理商： | XCS05-3BG144C |
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R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-20
DS060 (v1.5) March 2, 2000
Table 12: Boundary Scan Instructions
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-state. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contrib-
utes all three bits.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in
Figure 21
.
The device-specific pinout tables for the Spartan/XL
devices include the boundary scan locations for each IOB
pin.
Including Boundary Scan in a DesignIf boundary scan is only to be used during configuration, no
special schematic elements need be included in the sche-
matic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user func-
tions after configuration.
To indicate that boundary scan remain enabled after config-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in
Figure 22
.
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep TMS
High, and then apply whatever signal is desired to TDI and
TCK.
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configura-
tion, do either of the following:
TMS: Tie High to put the Test Access Port controller
in a benign RESET state
TCK: Tie High or Low
—
do not toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note, "
Boundary Scan in FPGA Devices
."
Instruction
I2
I1
0
0
0
0
Test
Selected
EXTEST
SAMPLE/
PRELOAD
USER 1
TDO Source
I/O Data
Source
DR
Pin/Logic
I0
0
1
DR
DR
0
1
0
BSCAN.
TDO1
BSCAN.
TDO2
User Logic
0
1
1
USER 2
User Logic
1
1
1
0
0
1
0
1 CONFIGURE
0
IDCODE
(Spartan-XL
only)
1
BYPASS
READBACK Readback Data
Pin/Logic
Disabled
—
DOUT
IDCODE
Register
1
1
Bypass Register
—
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MODE.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
(TDI end)
S6075_02
Figure 21: Boundary Scan Bit Sequence
TDI
TMS
TCK
TDO1
TDO2
TDO
DRCK
IDLE
SEL1
SEL2
TDI
TMS
TCK
TDO
BSCAN
To User
Logic
IBUF
Optional
From
User Logic
To User
Logic
X2675
Figure 22: Boundary Scan Schematic Example
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