System ACE MPM Solution
DS087 (v1.0) September 25, 2001
Advance Product Specification
1-800-255-777827
R
Quality and Reliability Characteristics
DC Characteristics Over Operating Conditions
Table 22
provides DC characteristics over operating conditions.
DC Input and Output Levels Over Operating Conditions
Three of the primary interfaces (the Boundary Scan inter-
face, the system control interface, and the target FPGA
interface) to the System ACE MPM have I/O level compati-
bility
control
pins.
See
Figure 2
FLASH_VCCO controls the internal Flash memory interface
and the Boundary Scan interface. FLASH_VCCO must be
connected to a 3.3V power supply. The Boundary Scan
ports (TCK, TMS, TDI, and TDO) and the internal Flash
and
Figure 4
.
memory interface pins follow the 3.3V input and output level
specification. CTRL_VCCO controls the system control
interface, and CFG_VCCO controls the target FPGA inter-
face. The input and output level specifications for the sys-
tem control and target FPGA interface pins depend on the
voltage connection to the CTRL_VCCO and CFG_VCCO
pins. See
Table 23
for the input and output level specifica-
tions for each VCCO voltage level.
AC Characteristics Over Operating Conditions
Table 24
provides the AC characteristics over operating conditions.
Table 22:
DC Characteristics Over Operating Conditions
Symbol
Description
Min
Max
Unit
V
DRINT1
I
CCINT1Q
I
CCINT2Q
I
L
C
IN
C
OUT
Data retention V
CCINT1
voltage
Quiescent V
CCINT1
supply current
Quiescent V
CCINT2
supply current
Input leakage current
1.5
V
200
mA
40
mA
-11
+11
N
A
Input capacitance
10
pF
Output capacitance
10
pF
Table 23:
DC Input and Output Levels Over Operating Conditions
VCCO
Voltage
Level
V
IL
, Min
-0.5V
V
IL
, Max
0.8V
V
IH
, Min
2.0V
V
IH
, Max
3.6V
V
OL
, Max
0.4V
V
OH
, Min
2.4V
I
OL
, Max
24 mA
I
OH
, Min
-24 mA
3.3V
2.5V
-0.5V
0.7V
1.7V
2.7V
0.4V
1.9V
12 mA
-12 mA
1.8V
-0.5V
35%
VCCO
65%
VCCO
1.95V
0.4V
VCCO -
0.4V
8 mA
-8 mA
Table 24:
AC Characteristics Over Operating Conditions
Timing Parameter
Description
Min
Max
Unit
F
SYS
T
SCL
T
SCH
T
SYSRESET
T
CYC
T
LC
T
HC
Maximum SYSCLK frequency
133
MHz
SYSCLK Low time
3.75
ns
SYSCLK High time
3.75
ns
Minimum SYSRESET pulse time
10
SYSCLK cycles
CFG_CCLK period
66.5
MHz
CFG_CCLK Low time
7.5
ns
CFG_CCLK High time
7.5
ns