
System ACE MPM Solution
DS087 (v1.0) September 25, 2001
Advance Product Specification
1-800-255-777815
R
Figure 7:
Example Slave-Serial Configuration for Identically Configured Xilinx FPGAs
DS087_07_091701
CFG_VCCO
CFG_DATA[0]
CFG_MODE[2]
CFG_MODE[1]
CFG_MODE[0]
CFG_CCLK
CFG_INIT
CFG_DONE
CFG_PROG
BUSY
FPGA
D0
M2
M1
M0
CCLK
INIT_B
DONE
PROG_B
FPGA
D0
M2
M1
M0
CCLK
INIT_B
DONE
PROG_B
To
Identical
FPGAs
*1 Supply voltage to CFG_VCCO that is compatible with the FPGA configuration pins.
*2 Combined ACC/WP on XCCACEM32; Separate WP and ACC on XCCACEM64.
CFG_DATA[0]
CFG_DATA[0]
System ACE MPM
FLASH_IO_LEVEL
WP *
2
ACC *
2
FCM_ENABLE
SYSCLK
BITSTRSEL[0-2]
STATUS[0-3]
SYSRESET
CLK Source
BITSTRSEL[0-2]
3.3 V
4.7 k
4.7 k
330
4.7 k
4.7 k
CFG_VCCO *
1
Table 10:
Slave-Serial FPGA Configuration Signals
System ACE MPM
Single
Slave-Serial Chain
Two
Slave-Serial Chains
Four
Slave-Serial Chains
Eight
Slave-Serial Chains
CFG_MODE[0]
M0 on all FPGAs
M0 on all FPGAs
M0 on all FPGAs
M0 on all FPGAs
CFG_MODE[1]
M1 on all FPGAs
M1 on all FPGAs
M1 on all FPGAs
M1 on all FPGAs
CFG_MODE[2]
M2 on all FPGAs
M2 on all FPGAs
M2 on all FPGAs
M2 on all FPGAs
CFG_CCLK
CCLK on all FPGAs
CCLK on all FPGAs
CCLK on all FPGAs
CCLK on all FPGAs
CFG_PROG
PROG_B on all
FPGAs
PROG_B on all
FPGAs
PROG_B on all
FPGAs
PROG_B on all
FPGAs
CFG_INIT
INIT_B on all FPGAs
INIT_B on all FPGAs
INIT_B on all FPGAs
INIT_B on all FPGAs
CFG_DONE
DONE on all FPGAs
DONE on all FPGAs
DONE on all FPGAs
DONE on all FPGAs
CFG_DATA[0]
DIN on first FPGA of
Chain 0
DIN on first FPGA of
Chain 0
DIN on first FPGA of
Chain 0
DIN on first FPGA of
Chain 0
CFG_DATA[1]
DIN on first FPGA of
Chain 1
DIN on first FPGA of
Chain 1
DIN on first FPGA of
Chain 1
CFG_DATA[2]
DIN on first FPGA of
Chain 2
DIN on first FPGA of
Chain 2
CFG_DATA[3]
DIN on first FPGA of
Chain 3
DIN on first FPGA of
Chain 3