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參數(shù)資料
| 型號： | XCCACEM32SERIES |
| 英文描述： | System ACE MPM Solution |
| 中文描述： | 系統(tǒng)ACE MPM的解決方案 |
| 文件頁數(shù)： | 13/29頁 |
| 文件大?。?/td> | 285K |
| 代理商： | XCCACEM32SERIES |
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System ACE MPM Solution
DS087 (v1.0) September 25, 2001
Advance Product Specification
1-800-255-777813
R
Slave-Serial
Similar to the Xilinx PROM solution, the System ACE MPM
is a single package solution that supports the configuration
of a single, cascaded chain of Slave-Serial FPGAs. With the
maximum configuration clock rate of 66 MHz, the System
ACE MPM is twice as fast as the nearest Xilinx PROM con-
figuration solution in the Slave-Serial mode.
The System ACE MPM has additional support for concur-
rently configuring multiple chains of Slave-Serial FPGAs.
Multiple data output pins on the System ACE MPM can con-
currently supply bitstreams for two to eight Slave-Serial
FPGA chains. Although each Slave-Serial chain has a max-
imum configuration clock rate of 66 MHz, the maximum bit
delivery rate of 66 Mb/s is maintained across all concurrent
Slave-Serial FPGA chains up to the cumulative maximum of
152 Mb/s. (152 Mb/s is the maximum read rate from the
AMD Flash memory in the System ACE MPM.)
In the Concurrent Slave-Serial configuration mode, the bit-
streams for the individual Slave-Serial chains are inter-
leaved and optimized for concurrent configuration of two,
four, or eight Slave-Serial FPGA chains. Configuration time
and storage requirements are optimal when the data stream
sizes are equivalent across all concurrent Slave-Serial
FPGA chains.
The connectivity between the System ACE MPM and
Slave-Serial FPGA chain is similar to the connectivity
between a Xilinx PROM and a Slave-Serial FPGA chain. All
configuration signals between Concurrent Slave-Serial
FPGA chains are common except that data for the first
chain originates from the System ACE MPM CFG_DATA[0]
pin, the data for the second chain originates from the
System ACE MPM CFG_DATA[1] pin, etc. See
Figure 5
for
a schematic of the Slave-Serial configuration signal connec-
tions, and see
Table 10
for a list of the Slave-Serial configu-
ration signals. The voltage compatibility for the System ACE
MPM configuration interface is configurable via the
CFG_VCCO pin. CFG_VCCO should be connected to a
voltage level that is compatible with the target FPGAs. Typi-
cally, CFG_VCCO is connected to either 3.3V or 2.5V. Con-
sult the target FPGA data sheet for an appropriate
configuration signal voltage level.
Identical configuration of multiple target FPGAs from one
bitstream can be achieved through the appropriate configu-
ration signal connections.
Figure 7
shows an example of
two FPGAs that are identically configured from a single bit-
stream.
Table 10
provides the Slave-Serial configuration
signals.
Configuration Done
CFG_DONE
DONE
DONE
DONE
SelectMAP/Slave-
Parallel Bus Read/Write
Signal
CFG_WRITE
RDWR_B
WRITE
WRITE
SelectMAP/Slave-
Parallel Bus Chip Select
Signal
CFG_CS[3:0]
CS_B
CS
CS
Table 9:
System ACE MPM and FPGA Configuration Signal Cross-Reference
FPGA Configuration
Signal
System ACE MPM
Virtex-II
Virtex/
Virtex-E
Spartan-II
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