參數(shù)資料
型號(hào)： XC3SD3400A-4CSG484LI
廠商： Xilinx Inc
文件頁數(shù)： 62/101頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 3 DSP 484CSGBGA
標(biāo)準(zhǔn)包裝： 84
系列： Spartan®-3A DSP
LAB/CLB數(shù)： 5968
邏輯元件/單元數(shù)： 53712
RAM 位總計(jì)： 2322432
輸入/輸出數(shù)： 309
門數(shù)： 3400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-FBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 484-CSPBGA
其它名稱： 122-1723
XC3SD3400A-4CSG484LI-ND
Spartan-3A DSP FPGA Family: Pinout Descriptions
DS610 (v3.0) October 4, 2010
Product Specification
63
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in Table 58.
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in Table 59. The table shows the
maximum number of single-ended I/O pins available,
assuming that all I/O-, INPUT-, DUAL-, VREF-, and
CLK-type pins are used as general-purpose I/O. AWAKE is
counted here as a dual-purpose I/O pin. Likewise, the table
shows the maximum number of differential pin-pairs
available on the package. Finally, the table shows how the
total maximum user-I/Os are distributed by pin type,
including the number of unconnected—N.C.—pins on the
device.
Not all I/O standards are supported on all I/O banks. The left
and right banks (I/O banks 1 and 3) support higher output
drive current than the top and bottom banks (I/O banks 0
and 2). Similarly, true differential output standards, such as
LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only
supported in the top or bottom banks (I/O banks 0 and 2).
Inputs are unrestricted. For more details, see the Using I/O
Resources chapter in UG331.
PWR
MGMT
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin
and is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is enabled
in the application, AWAKE is available as a user-I/O pin.
SUSPEND, AWAKE
JTAG
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX.
TDI, TMS, TCK, TDO
GND
Dedicated ground pin. The number of GND pins depends on the package used. All must be
connected.
GND
VCCAUX
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package
used. All must be connected. Set on board and using CONFIG VCCAUX constraint.
VCCAUX
VCCINT
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the
package used. All must be connected to +1.2V.
VCCINT
VCCO
Along with all the other VCCO pins in the same bank, this pin supplies power to the output
buffers within the I/O bank and sets the input threshold voltage for some I/O standards. All
must be connected.
VCCO_#
N.C.
This package pin is not connected in this specific device/package combination but may be
connected in larger devices in the same package.
N.C.
Notes:
1.
# = I/O bank number, an integer between 0 and 3.
Table 57: Types of Pins on Spartan-3A DSP FPGAs (Cont’d)
Type/Color
Code
Description
Pin Name(s) in Type
Table 58: Power and Ground Supply Pins by Package
Package
Device
VCCINT VCCAUX VCCO GND
CS484
XC3SD1800A
36
24
84
XC3SD3400A
36
24
84
FG676
XC3SD1800A
23
14
36
77
XC3SD3400A
36
24
40
100
Table 59: Maximum User I/O by Package
Package
Device
Maximum
User I/Os and
Input-Only
Maximum
Input-Only
Maximum
Differential
Pairs
All Possible I/Os by Type
I/O
INPUT
DUAL
VREF(1)
CLK
N.C.
CS484
XC3SD1800A
309
60
140
156
41
52
28
32
0
XC3SD3400A
309
60
140
156
41
52
28
32
0
FG676
XC3SD1800A
519
110
227
314
82
52
39
32
0
XC3SD3400A
469
60
213
314
34
52
37
32
0
Notes:
1.
Some VREFs are on INPUT pins. See pinout tables for details.
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