參數(shù)資料
型號(hào): XC3SD3400A-4CSG484LI
廠商: Xilinx Inc
文件頁(yè)數(shù): 2/101頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 DSP 484CSGBGA
標(biāo)準(zhǔn)包裝: 84
系列: Spartan®-3A DSP
LAB/CLB數(shù): 5968
邏輯元件/單元數(shù): 53712
RAM 位總計(jì): 2322432
輸入/輸出數(shù): 309
門數(shù): 3400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-FBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 484-CSPBGA
其它名稱: 122-1723
XC3SD3400A-4CSG484LI-ND
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
10
Power Supply Specifications
Table 4: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.4
1.0
V
VCCAUXT
Threshold for the VCCAUX supply
1.0
2.0
V
VCCO2T
Threshold for the VCCO Bank 2 supply
1.0
2.0
V
Notes:
1.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI
Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
Apply VCCINT last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more
information).
2.
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 5: Supply Voltage Ramp Rate
Symbol
Description
Min
Max
Units
VCCINTR
Ramp rate from GND to valid VCCINT supply level
0.2
100
ms
VCCAUXR
Ramp rate from GND to valid VCCAUX supply level
0.2
100
ms
VCCO2R
Ramp rate from GND to valid VCCO Bank 2 supply level
0.2
100
ms
Notes:
1.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI
Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
Apply VCCINT last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more
information).
2.
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 6: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data
Symbol
Description
Min
Units
VDRINT
VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
1.0
V
VDRAUX
VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
2.0
V
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