參數(shù)資料
型號(hào): XC3SD3400A-4CSG484LI
廠商: Xilinx Inc
文件頁數(shù): 59/101頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 DSP 484CSGBGA
標(biāo)準(zhǔn)包裝: 84
系列: Spartan®-3A DSP
LAB/CLB數(shù): 5968
邏輯元件/單元數(shù): 53712
RAM 位總計(jì): 2322432
輸入/輸出數(shù): 309
門數(shù): 3400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-FBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 484-CSPBGA
其它名稱: 122-1723
XC3SD3400A-4CSG484LI-ND
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
60
IEEE 1149.1/1532 JTAG Test Access Port Timing
X-Ref Target - Figure 15
Figure 15: JTAG Waveforms
Table 56: Timing for the JTAG(2) Test Access Port
Symbol
Description
All Speed
Grades
Units
Min
Max
Clock-to-Output Times
TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin
1.0
11.0
ns
Setup Times
TTDITCK
The time from the setup of data at the
TDI pin to the rising transition at the
TCK pin
All functions except those shown below
7.0
–ns
Boundary scan commands
(INTEST, EXTEST, SAMPLE)
13.0
TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
7.0
–ns
Hold Times
TTCKTDI
The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
All functions except those shown below
0
–ns
Configuration commands (CFG_IN, ISC_PROGRAM)
3.5
TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
0
–ns
Clock Timing
TCCH
The High pulse width at the TCK pin
All functions except ISC_DNA command
5
–ns
TCCL
The Low pulse width at the TCK pin
5
–ns
TCCHDNA The High pulse width at the TCK pin
During ISC_DNA command
10
10,000
ns
TCCLDNA The Low pulse width at the TCK pin
10
10,000
ns
FTCK
Frequency of the TCK signal
BYPASS or HIGHZ instructions
0
33
MHz
All operations except for BYPASS or HIGHZ instructions
20
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 7.
2.
For details on JTAG, see Chapter 9, “JTAG Configuraton Mode and Boundary-Scan” in UG332: Spartan-3 Generation Configuration User
Guide.
TCK
TTMSTCK
TMS
TDI
TDO
(Input)
(Output)
TTCKTMS
TTCKTDI
TTCKTDO
TTDITCK
DS099_06_090610
TCCH
TCCL
1/FTCK
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