- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4276 > XC3S400-4FG320I (Xilinx Inc)IC SPARTAN-3 FPGA 400K 320-FBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3S400-4FG320I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 200/272頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-3 FPGA 400K 320-FBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 896 |
| 邏輯元件/單元數(shù)： | 8064 |
| RAM 位總計(jì)： | 294912 |
| 輸入/輸出數(shù)： | 221 |
| 門數(shù)： | 400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 320-BGA |
| 供應(yīng)商設(shè)備封裝： | 320-FBGA（19x19） |
| 其它名稱： | Q3365683 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)當(dāng)前第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
33
The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV as described in Table 16. The clock outputs drive simultaneously; however, the
High Frequency mode only supports a subset of the outputs available in the Low Frequency mode. See DLL Frequency
Modes, page 35. Signals that initialize and report the state of the DLL are discussed in The Status Logic Component,
The clock signal supplied to the CLKIN input serves as a reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock skew, the common approach to using the DLL is as follows: The
CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either
internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via
a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. This
phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the
appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with
the CLKIN signal, it asserts the LOCKED output, indicating a “l(fā)ock” on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the DLL component through the use of the attributes described in
Table 17. Each attribute is described in detail in the sections that follow:
Table 16: DLL Signals
Signal
Direction
Description
Mode Support
Low
Frequency
High
Frequency
CLKIN
Input
Accepts original clock signal.
Yes
CLKFB
Input
Accepts either CLK0 or CLK2X as feed back signal. (Set CLK_FEEDBACK
attribute accordingly).
Yes
CLK0
Output
Generates clock signal with same frequency and phase as CLKIN.
Yes
CLK90
Output
Generates clock signal with same frequency as CLKIN, only phase-shifted 90°.
Yes
No
CLK180
Output
Generates clock signal with same frequency as CLKIN, only phase-shifted 180°.
Yes
CLK270
Output
Generates clock signal with same frequency as CLKIN, only phase-shifted 270°.
Yes
No
CLK2X
Output
Generates clock signal with same phase as CLKIN, only twice the frequency.
Yes
No
CLK2X180
Output
Generates clock signal with twice the frequency of CLKIN, phase-shifted 180°
with respect to CLKIN.
Yes
No
CLKDV
Output
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower
frequency clock signal that is phase-aligned to CLKIN.
Yes
Table 17: DLL Attributes
Attribute
Description
Values
CLK_FEEDBACK
Chooses either the CLK0 or CLK2X output to drive the CLKFB input
NONE, 1X, 2X
DLL_FREQUENCY_MODE
Chooses between High Frequency and Low Frequency modes
LOW, HIGH
CLKIN_DIVIDE_BY_2
Halves the frequency of the CLKIN signal just as it enters the DCM
TRUE, FALSE
CLKDV_DIVIDE
Selects constant used to divide the CLKIN input frequency to
generate the CLKDV output frequency
1.5, 2, 2.5, 3, 3.5, 4, 4.5,
5, 5.5, 6.0, 6.5, 7.0, 7.5,
8, 9, 10, 11, 12, 13, 14,
15, and 16.
DUTY_CYCLE_CORRECTION
Enables 50% duty cycle correction for the CLK0, CLK90, CLK180,
and CLK270 outputs
TRUE, FALSE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM12DREI | CONN EDGECARD 24POS .156 EYELET |
| ASC10DTEN | CONN EDGECARD 20POS .100 EYELET |
| XA3S500E-4FT256Q | IC FPGA SPARTAN-3E 256FPBGA |
| ASC10DTEH | CONN EDGECARD 20POS .100 EYELET |
| AMM30DRSI-S288 | CONN EDGECARD 60POS .156 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S400-4FG456C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 400K GATES 8064 CELLS 630MHZ 1.2V 456FBGA - Trays |
| XC3S400-4FG456I | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 400K GATES 8064 CELLS 630MHZ 1.2V 456FBGA - Trays |
| XC3S400-4FG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S400-4FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
| XC3S400-4FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。