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參數(shù)資料
| 型號： | XC3S1600E-5FGG484C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 170/227頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 1600K 484FBGA |
| 標準包裝： | 60 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 3688 |
| 邏輯元件/單元數(shù)： | 33192 |
| RAM 位總計： | 663552 |
| 輸入/輸出數(shù)： | 376 |
| 門數(shù)： | 1600000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 484-BBGA |
| 供應商設備封裝： | 484-FBGA |
| 配用： | HW-XA3S1600E-UNI-G-ND - KIT DEVELOPMENT AUTOMOTIVE ECU |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
47
Digital Clock Managers (DCMs)
For additional information, refer to the “Using Digital Clock
Managers (DCMs)” chapter in UG331.
Differences from the Spartan-3 Architecture
Spartan-3E FPGAs have two, four, or eight DCMs,
depending on device size.
The variable phase shifting feature functions differently
on Spartan-3E FPGAs than from Spartan-3 FPGAs.
The Spartan-3E DLLs support lower input frequencies,
down to 5 MHz. Spartan-3 DLLs support down to
18 MHz.
Overview
Spartan-3E FPGA Digital Clock Managers (DCMs) provide
flexible, complete control over clock frequency, phase shift
and skew. To accomplish this, the DCM employs a
Delay-Locked Loop (DLL), a fully digital control system that
uses feedback to maintain clock signal characteristics with a
high degree of precision despite normal variations in
operating temperature and voltage. This section provides a
fundamental description of the DCM.
The XC3S100E FPGA has two DCMs, one at the top and
one at the bottom of the device. The XC3S250E and
XC3S500E FPGAs each include four DCMs, two at the top
and two at the bottom. The XC3S1200E and XC3S1600E
FPGAs contain eight DCMs with two on each edge (see
also Figure 45). The DCM in Spartan-3E FPGAs is
surrounded by CLBs within the logic array and is no longer
located at the top and bottom of a column of block RAM as
in the Spartan-3 architecture. The Digital Clock Manager is
instantiated within a design using a “DCM” primitive.
The DCM supports three major functions:
Clock-skew Elimination: Clock skew within a system
occurs due to the different arrival times of a clock signal
at different points on the die, typically caused by the
clock signal distribution network. Clock skew increases
setup and hold time requirements and increases
clock-to-out times, all of which are undesirable in high
frequency applications. The DCM eliminates clock
skew by phase-aligning the output clock signal that it
generates with the incoming clock signal. This
mechanism effectively cancels out the clock distribution
delays.
Frequency Synthesis: The DCM can generate a wide
range of different output clock frequencies derived from
the incoming clock signal. This is accomplished by
either multiplying and/or dividing the frequency of the
input clock signal by any of several different factors.
Phase Shifting: The DCM provides the ability to shift
the phase of all its output clock signals with respect to
the input clock signal.
Although a single design primitive, the DCM consists of four
interrelated functional units: the Delay-Locked Loop (DLL),
the Digital Frequency Synthesizer (DFS), the Phase Shifter
(PS), and the Status Logic. Each component has its
associated signals, as shown in Figure 40.
X-Ref Target - Figure 40
Figure 40: DCM Functional Blocks and Associated Signals
DS099-2_07_101205
PSINCDEC
PSEN
PSCLK
CLKIN
CLKFB
RST
STATUS [7:0]
LOCKED
8
CLKFX180
CLKFX
CLK0
PSDONE
Clock
Distribution
Delay
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Status
Logic
DFS
DLL
Phase
Shifter
Del
a
y
S
tep
s
O
u
tp
u
t
S
ta
ge
Inp
u
t
S
ta
ge
DCM
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相關代理商/技術參數(shù) |
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|---|---|
| XC3S1600E-5FGG484I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
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