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參數(shù)資料
| 型號(hào)： | XC3S1000-5FTG256C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 26/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 1M 256-FTBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 1920 |
| 邏輯元件/單元數(shù)： | 17280 |
| RAM 位總計(jì)： | 442368 |
| 輸入/輸出數(shù)： | 173 |
| 門數(shù)： | 1000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 配用： | 122-1502-ND - KIT STARTER SPARTAN-3 PCI-E |
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Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
121
VREF: User I/O or Input Buffer Reference Voltage for Special Interface Standards
These pins are individual user-I/O pins unless collectively they supply an input reference voltage, VREF_#, for any SSTL,
HSTL, GTL, or GTLP I/Os implemented in the associated I/O bank. The ‘#’ character in the pin name represents an integer,
0 through 7, that indicates the associated I/O bank.
The VREF function becomes active for this pin whenever a signal standard requiring a reference voltage is used in the
associated bank. If used as a user I/O, then each pin behaves as an independent I/O described in the I/O type section. If
used for a reference voltage within a bank, then all VREF pins within the bank must be connected to the same reference
voltage.
Spartan-3 devices are designed and characterized to support certain I/O standards when VREF is connected to +1.25V,
+1.10V, +1.00V, +0.90V, +0.80V, and +0.75V. During configuration, the VREF pins behave exactly like user-I/O pins.
If designing for footprint compatibility across the range of devices in a specific package, and if the VREF_# pins within a bank
connect to an input reference voltage, then also connect any N.C. (not connected) pins on the smaller devices in that
package to the input reference voltage. More details are provided later for each package type.
N.C. Type: Unconnected Package Pins
Pins marked as “N.C.” are unconnected for the specific device/package combination. For other devices in this same
package, this pin may be used as an I/O or VREF connection. In both the pinout tables and the footprint diagrams,
unconnected pins are noted with either a black diamond symbol (
) or a black square symbol ().
If designing for footprint compatibility across multiple device densities, check the pin types of the other Spartan-3 devices
available in the same footprint. If the N.C. pin matches to VREF pins in other devices, and the VREF pins are used in the
associated I/O bank, then connect the N.C. to the VREF voltage source.
VCCO Type: Output Voltage Supply for I/O Bank
Each I/O bank has its own set of voltage supply pins that determines the output voltage for the output buffers in the I/O bank.
Furthermore, for some I/O standards such as LVCMOS, LVCMOS25, LVTTL, etc., VCCO sets the input threshold voltage on
the associated input buffers.
Spartan-3 devices are designed and characterized to support various I/O standards for VCCO values of +1.2V, +1.5V, +1.8V,
+2.5V, and +3.3V.
Most VCCO pins are labeled as VCCO_# where the ‘#’ symbol represents the associated I/O bank number, an integer
ranging from 0 to 7. In the 144-pin TQFP package (TQ144) however, the VCCO pins along an edge of the device are
combined into a single VCCO input. For example, the VCCO inputs for Bank 0 and Bank 1 along the top edge of the package
are combined and relabeled VCCO_TOP. The bottom, left, and right edges are similarly combined.
In Serial configuration mode, VCCO_4 must be at a level compatible with the attached configuration memory or data source.
In Parallel configuration mode, both VCCO_4 and VCCO_5 must be at the same compatible voltage level.
All VCCO inputs to a bank must be connected together and to the voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as described in XAPP623: Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors.
VCCINT Type: Voltage Supply for Internal Core Logic
Internal core logic circuits such as the configurable logic blocks (CLBs) and programmable interconnect operate from the
VCCINT voltage supply inputs. VCCINT must be +1.2V.
All VCCINT inputs must be connected together and to the +1.2V voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as described in XAPP623.
VCCAUX Type: Voltage Supply for Auxiliary Logic
The VCCAUX pins supply power to various auxiliary circuits, such as to the Digital Clock Managers (DCMs), the JTAG pins,
and to the dedicated configuration pins (CONFIG type). VCCAUX must be +2.5V.
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