參數(shù)資料
型號(hào): XC3S1000-5FTG256C
廠商: Xilinx Inc
文件頁數(shù): 227/272頁
文件大?。?/td> 0K
描述: SPARTAN-3A FPGA 1M 256-FTBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3
LAB/CLB數(shù): 1920
邏輯元件/單元數(shù): 17280
RAM 位總計(jì): 442368
輸入/輸出數(shù): 173
門數(shù): 1000000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
配用: 122-1502-ND - KIT STARTER SPARTAN-3 PCI-E
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DS099 (v3.1) June 27, 2013
Product Specification
58
Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DC Electrical Characteristics
In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as
follows:
Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics
of other families. Values are subject to change. Although speed grades with this designation are considered relatively
stable and conservative, some under-reporting might still occur. Use as estimates, not for production.
Preliminary: Based on complete early silicon characterization. Devices and speed grades with this designation are
intended to give a better indication of the expected performance of production silicon. The probability of under-reported
delays is greatly reduced compared to Advance data. Use as estimates, not for production.
Production: These specifications are approved only after silicon has been characterized over numerous production
lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes.
Parameter values are considered stable with no future changes expected.
Production-quality systems must only use FPGA designs compiled with a Production status speed file. FPGA designs
using a less mature speed file designation should only be used during system prototyping or preproduction qualification.
FPGA designs with speed files designated as Advance or Preliminary should not be used in a production-quality
system.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE
software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software
updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. The following
applies unless otherwise noted: The parameter values published in this module apply to all Spartan-3 devices. AC
and DC characteristics are specified using the same numbers for both commercial and industrial grades. All
parameters representing voltages are measured with respect to GND.
Mask and Fab Revisions
Some specifications list different values for one or more mask or fab revisions, indicated by the device top marking (see
Package Marking, page 5). The revision differences involve the power ramp rates, differential DC specifications, and DCM
characteristics. The most recent revision (mask rev E and GQ fab/geometry code) is errata-free with improved specifications
than earlier revisions.
Mask rev E with fab rev GQ has been shipping since 2005 (see XCN05009) and has been 100% of Xilinx Spartan-3 device
shipments since 2006. SCD 0974 was provided to ensure the receipt of the rev E silicon, but it is no longer needed. Parts
ordered under the SCD appended “0974” to the standard part number. For example, “XC3S50-4VQ100C” became
“XC3S50-4VQ100C0974”.
106
Spartan-3 FPGA Family:
DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
Product Specification
Table 28: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Max
Units
VCCINT
Internal supply voltage relative to GND
–0.5
1.32
V
VCCAUX
Auxiliary supply voltage relative to GND
–0.5
3.00
V
VCCO
Output driver supply voltage relative to GND
–0.5
3.75
V
VREF
Input reference voltage relative to GND
–0.5
VCCO +0.5
V
VIN
Voltage applied to all User I/O pins and
Dual-Purpose pins relative to GND(2,4)
Driver in a
high-impedance
state
Commercial
–0.95
4.4
V
Industrial
–0.85
4.3
Voltage applied to all Dedicated pins relative
to GND(3)
All temp. ranges
–0.5
VCCAUX + 0.5
V
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