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| 型號(hào)： | XC3030L-8VQ100I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 100 CLBS, 1500 GATES, 80 MHz, PQFP100 |
| 封裝： | PLASTIC, VQFP-100 |
| 文件頁(yè)數(shù)： | 34/76頁(yè) |
| 文件大小： | 731K |
| 代理商： | XC3030L-8VQ100I |
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R
XC3000 Series Field Programmable Gate Arrays
7-36
November 9, 1998 (Version 3.1)
Power
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated V
CC
and ground ring sur-
rounding the logic array provides power to the I/O drivers.
An independent matrix of V
CC
and groundlines supplies the
interior logic of the device. This power distribution grid pro-
vides a stable supply and ground for all internal logic, pro-
viding the external package power pins are all connected
and appropriately decoupled. Typically a 0.1-
μ
F capacitor
connected near the V
CC
and ground pins will provide ade-
quate decoupling.
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of driv-
ing as much as 25 to 30 times that current in a best case.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the ground pads. The I/O Block
output buffers have a slew-limited mode which should be
used where output rise and fall times are not speed critical.
Slew-limited outputs maintain their dc drive capability, but
generate less external reflections and internal noise.
1.00
0.80
0.60
0.40
0.20
SPECIFIED WORST-CASE VALUES
MAX COMMERCIAL (4.75 V)
MAX MILITARY (4.5 V)
– 55
MIN MILITARY (5.5 V)
MIN COMMERCIAL (4.75 V)
MIN COMMERCIAL (5.25 V)
TYPICAL COMMERCIAL
(+ 5.0 V, 25
°
C)
TYPICAL MILITARY
– 40
– 20
0
25
40
70
80
100
125
N
X6094
MIN MILITARY (4.5 V)
Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
S250
200
150
100
50
3 CLBs
(3-12)
4 CLBs
(4-16)
2 CLBs
(2-8)
1 CLB
(1-4)
XC3100A-3
XC3000A--6
CLB Levels:
Gate Levels:
300
Toggle
Rate
0
X7065
Figure 33: Clock Rate as a Function of Logic
Complexity
(Number of Combinational Levels between
Flip-Flops)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XC3030L-8VQ64C | 功能描述:IC FPGA C-TEMP 3.3V 64-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC3030L-8VQ64I | 功能描述:IC FPGA I-TEMP 3.3V 64-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC3042 | 制造商:Xilinx 功能描述: |
| XC3042-100CB100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC3042-100CB100C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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