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參數(shù)資料
| 型號： | XC2S600E-6FG456Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 60/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-IIE 456FPBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 3456 |
| 邏輯元件/單元數(shù)： | 15552 |
| RAM 位總計： | 294912 |
| 輸入/輸出數(shù)： | 329 |
| 門數(shù)： | 600000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 456-BBGA |
| 供應(yīng)商設(shè)備封裝： | 456-FBGA |
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DS077-4 (v3.0) August 9, 2013
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Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Spartan-IIE Package Pinouts
The Spartan-IIE family of FPGAs is available in five popu-
lar, low-cost packages, including plastic quad flat packs and
fine-pitch ball grid arrays. Family members have footprint
compatibility across devices provided in the same package,
with minor exceptions due to the smaller number of I/O in
smaller devices or due to LVDS/LVPECL pin pairing. The
Spartan-IIE family is not footprint compatible with any other
FPGA family. The following package-specific pinout tables
indicate function, pin, and bank information for all devices
available in that package. The pinouts follow the pad loca-
tions around the die, starting from pin 1 on the QFP pack-
ages.
Package Overview
Table 12 shows the five low-cost, space-saving production
package styles for the Spartan-IIE family.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “TQ144” package becomes
“TQG144” when ordered as the Pb-free option. Leaded
(non-Pb-free) packages may be available for selected
devices, with the same pin-out and without the "G" in the
ordering code; contact Xilinx sales for more information.
The mechanical dimensions of the standard and Pb-free
packages are similar, as shown in the mechanical drawings
provided in Table 13.
For additional package information, see UG112: Device
Package User Guide.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Material Declaration Data Sheets (MDDS) are also
available on the Xilinx web site for each package.
Table 12: Spartan-IIE Family Package Options
Package
Leads
Type
Maximum
I/O
Lead Pitch
(mm)
Footprint
Area (mm)
Height
(mm)
Mass(1)
(g)
TQ144 / TQG144
144
Thin Quad Flat Pack (TQFP)
102
0.5
22 x 22
1.60
1.4
PQ208 / PQG208
208
Plastic Quad Flat Pack (PQFP)
146
0.5
30.6 x 30.6
3.70
5.3
FT256 / FTG256
256
Fine-pitch Thin Ball Grid Array (FBGA)
182
1.0
17 x 17
1.55
1.0
FG456 / FGG456
456
Fine-pitch Ball Grid Array (FBGA)
329
1.0
23 x 23
2.60
2.2
FG676 / FGG676
676
Fine-pitch Ball Grid Array (FBGA)
514
1.0
27 x 27
2.60
3.1
Notes:
1.
Package mass is
±10%.
Table 13: Xilinx Package Documentation
Package
Drawing
MDDS
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG456
FGG456
FG676
FGG676
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S600E-6FG676C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| XC2S600E-6FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S600E-6FGG456C | 功能描述:IC SPARTAN-IIE FPGA 600K 456FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-IIE 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC2S600E-6FGG456I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S600E-6FGG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
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