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參數(shù)資料
| 型號(hào)： | XC2S600E-6FG456Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 34/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-IIE 456FPBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 3456 |
| 邏輯元件/單元數(shù)： | 15552 |
| RAM 位總計(jì)： | 294912 |
| 輸入/輸出數(shù)： | 329 |
| 門數(shù)： | 600000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 456-BBGA |
| 供應(yīng)商設(shè)備封裝： | 456-FBGA |
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DS077-3 (v3.0) August 9, 2013
31
Product Specification
2001–2013 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Definition of Terms
In this document, some specifications may be designated as Advance or Preliminary. These designations are based on the
more detailed timing information used by the development system and reported in the output files. These terms are defined
as follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values
are subject to change. Use as estimates, not for production.
Preliminary: Based on characterization. Further changes are not expected.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications. All specifications
are subject to change without notice.
DC Specifications
Absolute Maximum Ratings(1)
Spartan-IIE FPGA Family:
DC and Switching Characteristics
DS077-3 (v3.0) August 9, 2013
0
Product Specification
Symbol
Description
Min
Max
Units
VCCINT
Supply voltage relative to GND
–0.5
2.0
V
VCCO
Supply voltage relative to GND
–0.5
4.0
V
VREF
Input reference voltage
–0.5
4.0
V
VIN
Input voltage relative to GND(2,3)
–0.5
4.0
V
VTS
Voltage applied to 3-state output(3)
–0.5
4.0
V
TSTG
Storage temperature (ambient)
–65
+150
°C
TJ
Junction temperature
-
+125
°C
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2.
VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day).
3.
Maximum DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and undershoot must be limited to –0.5V or 10 mA,
whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to –2.0V or overshoot
to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
4.
For soldering guidelines, see the Packaging Information on the Xilinx website.
R
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S600E-6FG676C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| XC2S600E-6FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S600E-6FGG456C | 功能描述:IC SPARTAN-IIE FPGA 600K 456FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC2S600E-6FGG456I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S600E-6FGG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
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