參數(shù)資料
型號(hào)： XA-SCC
廠商： NXP Semiconductors N.V.
英文描述： CMOS 16-bit communications microcontroller
中文描述： 的CMOS 16位微控制器的通信
文件頁(yè)數(shù)： 15/42頁(yè)
文件大小： 229K
代理商： XA-SCC
Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
15
MMR Name
Reset
Value
Description
Address
Offset
Size
Read/Write or
Read Only
Buffer Base Register Ch.1 Tx
R/W
8
154h
Wrap Reload Value for A15–A8, A7–A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Byte0 & 1
Byte2 & 3
Control Register
Control & Status Register
Points to 64K data segment
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Byte0 & 1
Byte2 & 3
Control Register
Control & Status Register
Points to 64K data segment
Wrap Reload Value for A15 –A8
A7–A0 reloaded to zero by hardware
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Byte0 & 1
Byte2 & 3
RESERVED for future DMA
00h
Buffer Bound Register Ch.1 Tx
Address Pointer Reg Ch.1 Tx
Byte Count Register Ch.1 Tx
R/W
R/W
R/W
16
16
16
156h
158h
15Ah
0000h
0000h
0000h
Data FIFO Register Ch.1 Lo Tx
Data FIFO Register Ch.1 Hi Tx
DMA Control Register Ch.2 Tx
FIFO Control & Status Register Ch.2 Tx
Segment Register Ch.2 Tx
Buffer Base Register Ch.2 Tx
R/W
R/W
R/W
R/W
R/W
R/W
16
16
8
8
8
8
15Ch
15Eh
160h
161h
162h
164h
0000h
0000h
00h
00h
00h
00h
Buffer Bound Register Ch.2 Tx
Address Pointer Reg Ch.2 Tx
Byte Count Register Ch.2 Tx
R/W
R/W
R/W
16
16
16
166h
168h
16Ah
0000h
0000h
0000h
Data FIFO Register Ch.2 Lo Tx
Data FIFO Register Ch.2 Hi Tx
DMA Control Register Ch.3 Tx
FIFO Control & Status Register Ch.3 Tx
Segment Register Ch. 3 Tx
Buffer Base Register Ch. 3 Tx
R/W
R/W
R/W
R/W
R/W
R/W
16
16
8
8
8
8
16Ch
16Eh
170h
171h
172h
174h
0000h
0000h
00h
00h
00h
00h
Buffer Bound Register Ch.3 Tx
Address Pointer Reg Ch.3 Tx
Byte Count Register Ch.3 Tx
R/W
R/W
R/W
16
16
16
176h
178h
17Ah
0000h
0000h
0000h
Data FIFO Register Ch.3Lo Tx
Data FIFO Register Ch.3 Hi Tx
R/W
R/W
R/W
16
16
17Ch
17Eh
180–1FEh
0000h
0000h
—
Miscellaneous DMA Registers
8
8
8
8
16
V.54/2047 Registers
8
8
8
8
8
8
8
8
8
8
Rx Character Time Out Register Ch.0
Rx Character Time Out Register Ch.1
Rx Character Time Out Register Ch.2
Rx Character Time Out Register Ch.3
Global DMA Interrupt Register
R/W
R/W
R/W
R/W
R/W
200h
202h
204h
206h
210h
0 value disables counter interrupt.
Same as above, for Rx1
Same as above, for Rx2
Same as above, for Rx3
DMA Interrupt Flags
00h
00h
00h
00h
0000h
VACS
VACFG
VATCL
VATCH
VAEC
VBCS
VBCFG
VBTCL
VBTCH
VBEC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
240h
241h
242h
243h
244h
248h
249h
24Ah
24Bh
24Ch
V.54 2047 Unit A Control & Status
V.54 2047 Unit A Configuration
V.54 2047 Unit A Threshold Cntr Lo
V.54 2047 Unit A Threshold Cntr Hi
V.54 2047 Unit A Error Counter
V.54 2047 Unit B Control & Status
V.54 2047 Unit B Configuration
V.54 2047 Unit B Threshold Cntr Lo
V.54 2047 Unit B Threshold Cntr Hi
V.54 2047 Unit B Error Counter
00h
—
—
—
—
00h
—
—
—
—
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