參數(shù)資料
型號： XA-SCC
廠商： NXP Semiconductors N.V.
英文描述： CMOS 16-bit communications microcontroller
中文描述： 的CMOS 16位微控制器的通信
文件頁數(shù)： 12/42頁
文件大?。?/td> 229K
代理商： XA-SCC
Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
12
MMR Name
Reset
Value
Description
Address
Offset
Size
Read/Write or
Read Only
SCC1 Write Register 13
SCC1 Write Register 14
SCC1 Write Register 15
SCC1 Write Register 16
SCC1 Write Register 17
SCC1 Read Register 0
SCC1 Read Register 1
Reserved
SCC1 Read Register 3
see WR16 and 17
SCC1 Read Register 6
SCC1 Read Register 7
SCC1 Read Register 8
Reserved
SCC1 Read Register 10
Reserved
R/W
R/W
R/W
R/W
R/W
RO
RO
8
8
8
8
8
8
8
85Ah
85Ch
85Eh
868h
86Ah
860h
862h
864h
866h
868–86Ah
86Ch
86Eh
870h
872h
874h
876–87Eh
Upper Byte of Baud rate time constant
Misc. Control bits
External/Status interrupt control
Match Character 2 (WR16)
Match Character 3 (WR17)
Tx/Rx buffer and external status
Receive condition status/residue code
00h
xx
f8h
00h
00h
—
—
—
—
—
—
—
—
—
—
—
RO
8
Interrupt Pending Bits
see WR16 and WR17 above
SDLC byte count low register
SDLC byte count high & FIFO status
Receive Buffer
RO
RO
RO
8
8
8
RO
8
Loop/clock status
SCC2 Registers
8
8
8
8
8
8
8
SCC2 Write Register 0
SCC2 Write Register 1
SCC2 Write Register 2
SCC2 Write Register 3
SCC2 Write Register 4
SCC2 Write Register 5
SCC2 Write Register 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
880h
882h
884h
886h
888h
88Ah
88Ch
Command register
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx misc. parameters & mode
Tx. parameter and control
Sync character or SDLC address field or Match
Character 0
Sync character or SDLC flag or Match Character 1
Transmit Data Buffer
Master Interrupt control
Misc. Tx/Rx control register
Clock Mode Control
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Misc. Control bits
External/Status interrupt control
Match Character 2 (wr16)
Match Character 3 (wr17)
Tx/Rx buffer and external status
Receive condition status/residue code
00h
xx
xx
00h
00h
00h
00h
SCC2 Write Register 7
SCC2 Write Register 8
SCC2 Write Register 9
SCC2 Write Register 10
SCC2 Write Register 11
SCC2 Write Register 12
SCC2 Write Register 13
SCC2 Write Register 14
SCC2 Write Register 15
SCC2 Write Register 16
SCC2 Write Register 17
SCC2 Read Register 0
SCC2 Read Register 1
Reserved
SCC2 Read Register 3
see WR16 and 17
SCC2 Read Register 6
SCC2 Read Register 7
SCC2 Read Register 8
Reserved
SCC2 Read Register 10
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
8
8
8
8
8
8
8
8
8
8
8
8
8
88Eh
890h
892h
894h
896h
898h
89Ah
89Ch
89Eh
8A8h
8AAh
8A0h
8A2h
8A4h
8A6h
8A8–8AAh
8ACh
8AEh
8B0h
8B2h
8B4h
8B6–8BEh
xx
xx
xx
00h
xx
00h
00h
xx
f8h
00h
00h
—
—
—
—
—
—
—
—
—
—
—
RO
8
Interrupt Pending Bits
see WR16 and WR17 above
SDLC byte count low register
SDLC byte count high & FIFO status
Receive Buffer
RO
RO
RO
8
8
8
RO
8
Loop/clock status
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