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參數(shù)資料
| 型號(hào)： | XA-H4 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 16-bit microcontroller |
| 中文描述： | 單片16位微控制器 |
| 文件頁(yè)數(shù)： | 29/42頁(yè) |
| 文件大小： | 225K |
| 代理商： | XA-H4 |
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Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
29
PRELIMINARY AC ELECTRICAL CHARACTERISTICS (5.0 V +/–10%)
V
DD
= 5.0 V +/– 10%; T
amb
= –40
°
C to +85
°
C (industrial)
Symbol
Fig re
Figure
Parameter
Limits
Unit
Min
Max
All Cycles
F
C
t
C
System Clock Frequency
0
30
MHz
23
System Clock Period = 1/FC
33.33
–
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
t
AVSL
t
CHAH
t
CHAV
t
CHSH
t
CHSL
t
CODH
t
CPWH
t
CPWL
23
XTALIN High Time
t
C
* 0.5
t
C
* 0.4
–
–
ns
23
XTALIN Low Time
–
ns
23
XTALIN Rise Time
5
ns
23
XTALIN Fall Time
–
5
ns
All
Address Valid to Strobe low
Address hold after ClkOut rising edge
9
t
C
– 21
1
–
ns
All
–
ns
All
Delay from ClkOut rising edge to address valid
Delay from ClkOut rising edge to Strobe High
9
Delay from ClkOut rising edge to Strobe Low
9
–
25
ns
All
1
21
ns
All
1
19
ns
24
ClkOut Duty Cycle High (into 40 pF max.)
t
CHCX
–7
t
C
– 12
t
C
– 10
t
CHCX
+3
–
ns
11, 12, 17, 18, 19, 20
CAS Pulse Width High
ns
11, 19
CAS Pulse Width Low
–
ns
All DRAM Cycles
t
RP
22
RAS precharge time, thus minimum RAS high time
8
(n * t
C
) – 16
8
–
ns
Generic Data Read Only
t
AHDR
7, 14
Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at
end of Generic Data Read Cycle (not code fetch)
t
C
– 12
–
ns
Data Read and Instruction Fetch Cycles
t
DIS
7, 8, 10, 11, 12, 14, 15,
17, 18, 19
7, 8, 10, 14, 15, 17, 18
Data In Valid setup to ClkOut rising edge
25
–
ns
t
DIH
t
OHDE
Data In Valid hold after ClkOut rising edge
2
0
–
ns
8, 10, 11, 14, 18
OE high to XA Data Bus Driver Enable
t
C
– 14
–
ns
Write Cycles
t
CHDV
t
DVSL
t
SHAH
t
SHDH
9, 13
Clock High to Data Valid
–
25
ns
16, 20
Data Valid prior to Strobe Low
t
C
– 23
t
C
– 25
t
C
– 25
–
ns
9, 16
Minimum Address Hold Time after strobe goes inactive
–
ns
9, 16
Data hold after strobes (CS and BHE/BLE) high
–
ns
Refresh
t
CLRL
21
CAS low to RAS low
t
C
– 15
–
ns
Wait Input
t
WS
t
WH
25
WAIT setup (stable high or low) to ClkOut rising edge
20
–
ns
25
WAIT hold (stable high or low) after ClkOut rising edge
0
–
ns
NOTE:
1. See notes after the 3.3 V AC Timing Table
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