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參數(shù)資料
| 型號： | XA-H4 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 16-bit microcontroller |
| 中文描述： | 單片16位微控制器 |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 225K |
| 代理商： | XA-H4 |
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Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
25
The XA-H4 has a standard XA CPU Interrupt Controller,
implemented with 15 Maskable Event Interrupts. Event Interrupts
are defined as maskable interrupts usually generated by hardware
events. However, in the XA-H4, 4 of the 15 Event Interrupts are
generated by software writing directly to the interrupt flag bit. These
4 interrupts are referred to as “High Priority Software Interrupts.”
See the IC25 XA Data Handbookfor a full explanation of the
exception structure, including event interrupts, of the XA CPU.
Because the High Priority Software Interrupts are not implemented
on all XA derivitives, they are explained in the XA-H4 User Manual
SU01276
XA Core
Interrupt Controller
Interrupt
Enable/
Disable Bits
Master
Enable
“EA”
Interrupt
To XA CPU
DMAH
DMAL
4
DMA
Interrupts
USART0/
USART1
Timer 0
Timer 1
High Priority
Software Ints
HSWR 3–0
CTS0
CD0
CTS1
INT1
INT0
INT2
USART2/
USART3
CD1_INT2
CTS2
CD2
CTS3
CD3
Autobaud
3–0
Figure 6. XA-H4 Interrupt Structure Overview
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