參數(shù)資料
型號(hào)： XA-H4
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 16-bit microcontroller
中文描述： 單片16位微控制器
文件頁(yè)數(shù)： 13/42頁(yè)
文件大?。?/td> 225K
代理商： XA-H4
Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
13
Table 3. Memory Mapped Registers (MMR)
MMR Name
Read/Write
or Read Only
Size
Address
Offset
Description
Reset
Value
USART0 Registers
8
800h
8
802h
8
804h
8
806h
8
808h
8
80Ah
8
80Ch
8
80Eh
8
810h
8
812h
8
814h
8
816h
8
818h
8
81Ah
8
81Ch
8
81Eh
8
828h
8
82Ah
8
820h
8
822h
824h
8
826h
828–82Ah
8
82Ch
8
82Eh
8
830h
832h
8
834h
836-83Eh
USART0 Write Register 0
USART0 Write Register 1
USART0 Write Register 2
USART0 Write Register 3
USART0 Write Register 4
USART0 Write Register 5
USART0 Write Register 6 (XA-H4 only)
USART0 Write Register 7
USART0 Write Register 8
USART0 Write Register 9
USART0 Write Register 10
USART0 Write Register 11
USART0 Write Register 12
USART0 Write Register 13
USART0 Write Register 14
USART0 Write Register 15
USART0 Write Register 16
USART0 Write Register 17
USART0 Read Register 0
USART0 Read Register 1
Reserved – do not write
USART0 Read Register 3
see WR16 and 17
USART0 Read Register 6
USART0 Read Register 7
USART0 Read Register 8
Reserved
USART0 Read Register 10
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Command register
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx miscellaneous parameters & mode
Tx parameter and control
00h
xx
xx
00h
00h
00h
00h
xx
xx
xx
00h
xx
00h
00h
xx
f8h
00h
00h
HDLC/SDLC address field or asynch Match Character 0
HDLC/SDLC flag or Match Character 1
Transmit Data Buffer
Master Interrupt control
Miscellaneous Tx/Rx control register
Clock Mode Control
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Miscellaneous Control bits
External/Status interrupt control
Match Character 2 (WR16)
Match Character 3 (WR17)
Tx/Rx buffer and external status
Receive condition status/residue code
–
RO
Interrupt Pending Bits
see WR16 and 17 above
SDLC byte count low register
SDLC byte count high and FIFO status
Receive Buffer
RO
RO
RO
RO
Loop/clock status
–
USART1 Registers
8
840h
8
842h
8
844h
8
846h
8
848h
8
84Ah
8
84Ch
8
84Eh
8
850h
8
852h
8
854h
8
856h
8
858h
8
85Ah
USART1 Write Register 0
USART1 Write Register 1
USART1 Write Register 2
USART1 Write Register 3
USART1 Write Register 4
USART1 Write Register 5
USART1 Write Register 6
USART1 Write Register 7
USART1 Write Register 8
USART1 Write Register 9
USART1 Write Register 10
USART1 Write Register 11
USART1 Write Register 12
USART1 Write Register 13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Command register
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx miscellaneous parameters & mode
Tx parameter and control
HDLC/SDLC address field or Match Character 0
HDLC/SDLC flag or async Match Character 1
Transmit Data Buffer
Master Interrupt control
Miscellaneous Tx/Rx control register
Clock Mode Control
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
00h
xx
xx
00h
00h
00h
00h
xx
xx
xx
00h
xx
00h
00h
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