參數(shù)資料
型號(hào)： XA-H4
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 16-bit microcontroller
中文描述： 單片16位微控制器
文件頁(yè)數(shù)： 21/42頁(yè)
文件大?。?/td> 225K
代理商： XA-H4
Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
21
Clock Output
The ClkOut pin allows easier external bus interfacing in some
situations. This output reflects the XTALIn clock input to the XA
(referred to internally as CClk or System Clock), but is delayed to
match the external bus outputs and strobes. The default is for
ClkOut to be output enabled at reset, but it may be turned off
(tri-state disabled) by software via the MICFG MMR.
WARNING:
The capacitive loading on this output must not
exceed 40 pf.
CS
OE
A16–A0
D7–D0
WE
A9–A0
D15–D0
SU01275
CS0
CS1
OE
A19–A0
D15–D0
CS3
BLE
BHE
WE
XA-H4
RAS
CASL
CASH
WE
A15–A1
D15–D0
32 k x 16 SRAM
1 M x 16 DRAM
(MT4C1M16C3)
D15–D0
NOTE:
The 16-bit wide RAM does not need the A0 pin from the processor. During byte writes to the RAM, the A0 value will cause
either BLE or BHE pin to go active from the XA-H3, but not to both. For all Word Writes, Word Reads, Code Fetches, and
Byte Reads, both BLE and BHE will go active.During DRAM cycles only, the appropriate CAS Address will be multiplexed
onto pins A17 – A7 after the assertion of RAS and prior to the assertion of BHE (CASH) and BLE (CASL.) See AC timing
diagrams and the XA-H4 User Manualfor complete details.
CS2
A17–A8
D15–D0
A15–A1
OE
256 k x 16 DRAM
(HM514260DI)
128 k x 8 ROM
CASH
CASL
RAS
WE
A8–A0
D15–D0
OE
CASH
CASL
RAS
A17–A9
D15–D0
A16–A0
D7–D0
Figure 4. Typical system bus configuration
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