Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
14
MMR Name
Reset
Value
Description
Address
Offset
Size
Read/Write
or Read Only
USART1 Write Register 14
USART1 Write Register 15
USART1 Write Register 16
USART1 Write Register 17
USART1 Read Register 0
USART1 Read Register 1
Reserved
USART1 Read Register 3
see WR16 and WR17
USART1 Read Register 6
USART1 Read Register 7
USART1 Read Register 8
Reserved
USART1 Read Register 10
Reserved
R/W
R/W
R/W
R/W
RO
RO
8
8
8
8
8
8
85Ch
85Eh
868h
86Ah
860h
862h
864h
866
86Ch
86Eh
86Eh
870h
872h
874h
876-87Eh
Miscellaneous Control bits
External/Status interrupt control
Match Character 2 (WR16)
Match Character 3 (WR17)
Tx/Rx buffer and external status
Receive condition status/residue code
xx
f8h
00h
00h
RO
8
8
8
8
8
Interrupt Pending Bits
see WR16 and 17 above
SDLC byte count low register
SDLC byte count high and FIFO status
Receive Buffer
RO
RO
RO
RO
8
Loop/clock status
USART2 Registers
8
880h
8
882h
8
884h
8
886h
8
888h
8
88Ah
8
88Ch
8
88Eh
8
890h
8
892h
8
894h
8
896h
8
898h
8
89Ah
8
89Ch
8
89Eh
8
8A8h
8
8AAh
8
8A0h
8
8A2h
8A4h
8
8A6h
8
8ACh
8
8AEh
8
8AEh
8
8B0h
8B2h
8
8B4h
8B6-8BEh
USART2 Write Register 0
USART2 Write Register 1
USART2 Write Register 2
USART2 Write Register 3
USART2 Write Register 4
USART2 Write Register 5
USART2 Write Register 6
USART2 Write Register 7
USART2 Write Register 8
USART2 Write Register 9
USART2 Write Register 10
USART2 Write Register 11
USART2 Write Register 12
USART2 Write Register 13
USART2 Write Register 14
USART2 Write Register 15
USART2 Write Register 16
USART2 Write Register 17
USART2 Read Register 0
USART2 Read Register 1
Reserved
USART2 Read Register 3
see WR16 and WR17
USART2 Read Register 6
USART2 Read Register 7
USART2 Read Register 8
Reserved
USART2 Read Register 10
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Command register
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx miscellaneous parameters & mode
Tx parameter and control
HDLC/SDLC address field or Match Character 0
HDLC/SDLC flag or Match Character 1
Transmit Data Buffer
Master Interrupt control
Miscellaneous Tx/Rx control register
Clock Mode Control
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Miscellaneous Control bits
External/Status interrupt control
Match Character 2 (WR16)
Match Character 3 (WR17)
Tx/Rx buffer and external status
Receive condition status
00h
xx
xx
00h
00h
00h
00h
xx
xx
xx
00h
xx
00h
00h
xx
f8h
00h
00h
RO
Interrupt Pending Bits
see WR16 and 17 above
SDLC byte count low register
SDLC byte count high and FIFO status
Receive Buffer
RO
RO
RO
RO
Loop/clock status