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參數(shù)資料
| 型號： | XA-C3 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| 中文描述： | 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce |
| 文件頁數(shù)： | 31/68頁 |
| 文件大小： | 368K |
| 代理商： | XA-C3 |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
24
RST/Pin Properties and Requirements
Active LOW for improved noise immunity
Schmitt Trigger with Threshold = 0.7 Vdd
RST
/
must be low for the longer of 10
μ
s or 10 clocks
If EA
/
= 1, all Port pins are set to Quasi–Bidirectional mode
If EA
/
= 0, all External Bus pins are set to Push–Pull mode
Power-On Reset
Must be > 10 msec to allow the on–chip oscillator to stabilize
Other Reset Effects
Register File is zeroed except [R7] USP/SSP is set to 100h
Internal DATA RAM is not affected
All maskable interrupts are disabled
DS, ES, CS, SSEL, PZ, CM, PT0 and PT1 are zeroed
The Watchdog Timer is turned ON
Reset Timing
The EA
/
pin is sampled on the rising edge of the Reset (RST
/
) pulse.
The result of this sampling determines whether the device is to
begin execution from internal or External PROGRAM memory.
Specifically, if EA
/
is pulled high, the XA starts in Single–Chip mode.
Lastly, after RST
/
is released, the {WAIT ; V
pp
; EA
/
} pin becomes a
bus WAIT signal for External bus transactions.
P3.5 is weakly pulled high whenever RST/ is asserted. Given EA/
is used at RESET to request code starts from External memory, this
weak pull up assures the PXAC3 will set–up a 16 bit External bus.
Thus, if External code operation is desired, the User must NEVER
put a LOW on P3.5 during RESET.
Note: EA/ must be held for eight equivalent oscillator clock periods
after RST/ is deasserted (i.e., after RST/ returns to ONE) to
guarantee that the desired EA/ value is latched correctly.
The relationship of EA/ timing with respect to both RST/ and ALE
signals is shown in Figure 20.
RST/
EA/
ALE
< 1 CLK
At least 8 equivalent CLK periods
At least 5 equivalent CLK periods
EA/ Held Stable
Alternate “Hold” reference
SU01333
Figure 20. EA/ Timing Diagram
Power Reduction Modes
The XA–C3 supports Idle and Power–Down modes of power
reduction. The Idle mode leaves some peripherals running to allow
them to wake up the processor when an interrupt is generated. The
Power–Down mode stops the oscillator in order to minimize power.
The processor can be made to exit Power–Down mode via Reset or
one of the External interrupt inputs. In order to use an External
interrupt to re–activate the XA while in Power–Down mode, the
External interrupt must be enabled and be configured to
level–sensitive mode. In Power–Down mode, the power supply
voltage may be reduced to the RAM keep–alive voltage (2V),
retaining the RAM, register, and SFR values at the point where the
Power–Down mode was entered.
Interrupts
Interrupt Types
There are four types of interrupts:
Event Interrupts
– service peripherals such as UARTs and
timers.
Software Interrupts
– demote the priority level of a running Event
Interrupt below the lowest Event priority level (i.e., 9), thereby
permitting lower priority Event Interrupts to run.
Trap Interrupts
–accomplish multi–tasking services, such as
RTOS, via non–maskable interrupts.
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