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| 型號： | XA-C3 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| 中文描述： | 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce |
| 文件頁數(shù)： | 17/68頁 |
| 文件大?。?/td> | 368K |
| 代理商： | XA-C3 |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
10
NAME
RESET
BIT FUNCTIONS AND BIT ADDRESSES
SFR
DESCRIPTION
VALUE
0
1
2
3
4
5
6
7
ADDRESS
30F
30E
30D
30C
30B
30A
309
308
S0STAT*
S0BUF
S0ADDR
Serial port 0 extended status
Serial port 0 buffer register
Serial port 0 address register
Serial port 0 address enable
register
System configuration register
421h
460h
461h
–
–
–
–
FE0
BR0
OE0
STINT0
00h
xxh
00h
S0ADEN
462h
00h
SCR
440h
–
–
–
–
PT1
PT0
CM
PZ
00h
21F
21E
21D
21C
21B
21A
219
218
SSEL*
SWE
Segment selection register
Software Interrupt Enable
403h
47Ah
ESWEN
R6SEG
R5SEG
R4SEG
R3SEG
R2SEG
R1SEG
R0SEG
00h
00h
–
SWE7
SWE6
SWE5
SWE4
SWE3
SWE2
SWE1
357
356
355
354
353
352
351
350
SWR*
Software Interrupt Request
42Ah
–
SWR7
SWR6
SWR5
SWR4
SWR3
SWR2
SWR1
00h
2C7
2C6
2C5
2C4
2C3
2C2
2C1
C2 or
T2
/
2C9
2C0
CP or
RL2
/
2C8
T2CON*
Timer 2 control register
418h
TF2
EXF2
RCLK0
TCLK0
EXEN2
TR2
00h
2CF
2CE
2CD
2CC
2CB
2CA
T2MOD*
TH2
TL2
Timer 2 mode control
Timer 2 high byte
Timer 2 low byte
Timer 2 capture register, high
byte
Timer 2 capture register, low
byte
419h
459h
458h
–
–
–
–
–
–
T2OE
DCEN
00h
00h
00h
T2CAPH
45Bh
00h
T2CAPL
45Ah
00h
287
286
285
284
283
282
281
280
TCON*
TH0
TH1
TL0
TL1
TMOD
Timer 0 and 1 control register
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
Timer 0 and 1 mode control
410h
451h
453h
450h
452h
45Ch
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
00h
00h
00h
00h
00h
GATE1
C1 or T1
/
M1
M0
GATE0
C0 or T0
/
M1
M0
28F
28E
28D
28C
28B
28A
289
288
TSTAT*
Timer 0 and 1 extended status
411h
–
–
–
–
–
T1OE
–
T0OE
00h
2FF
2FE
2FD
2FC
2FB
2FA
2F9
2F8
WDCON*
WDL
WFEED1
WFEED2
Watchdog control register
Watchdog timer reload
Watchdog feed 1
Watchdog feed 2
41Fh
45Fh
45Dh
45Eh
PRE2
PRE1
PRE0
–
–
WDRUN
WDTOF
–
Note 6
00h
xxh
xxh
NOTES:
1. Users should never write to the BCR register.
2. Users must ALWAYS INITIALIZE (Write) 00h to this register.
3. Port configurations default to Quasi–Bidirectional when the XA begins execution from Internal code memory after Reset, based on the
condition found on the EA
/
pin. Thus, all PnCFGA registers will contain FFh and PnCFGB registers will contain 00h. When the XA begins
execution using External code memory, the default configuration for pins that are associated with the External bus will be Push–Pull. The
PnCFGA and PnCFGB register contents will reflect this difference.
4. SFR is loaded from the Reset vector.
5. All bits except F1, F0, and P are loaded from the Reset vector. Those bits are all 0.
6. The WDCON Reset value is E6h for a Watchdog Reset, E4h for all other Reset causes. The Watchdog is always turned ON as one
consequence of RST
/
. Therefore, the user should turn OFF the Watchdog if immediate Watchdog operation is not desired: See the
Watchdog Timer section in this Data Sheet for a recommended code example.
GENERAL NOTES:
– SFRs marked with an asterisk (*) are bit–addressable.
– The XA–C3 implements an 8–bit SFR bus, as stated in Chapter 8 of the XA User Guide All SFR accesses must be 8–bit operations.
Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen–bit SFR reads will return undefined data in the upper byte.
– Unimplemented bits in SFRs (indicated by ”–”} are unknown at all times. Ones should not be written to these bits since they may be used for
other purposes in future XA derivatives. In general, the Reset value shown for these unimplemented bits is 00h.
– The XA guards writes to all SFR bits that can be modified by hardware, including all SFR resident interrupt flags, as well as the WDTOF bit in
WDCON. This mechanism, called Read–Modify–Write Lockout, prevents loss of an interrupt (or other status) flag if a bit is written to directly
by hardware between the read and write of an instruction that performs a read–modify–write operation.
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