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| 型號： | XA-C3 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| 中文描述： | 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce |
| 文件頁數(shù)： | 30/68頁 |
| 文件大?。?/td> | 368K |
| 代理商： | XA-C3 |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
23
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP
BIT
DATA BYTE
ONLY IN
MODE 2, 3
START
BIT
SU01331
—
—
—
—
FE0
BR0
OE0
STINT0
S0STAT
if 0, sets FE
Figure 17. UART Framing Error Detection
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
S0CON
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
1
1
0
COMPARATOR
1
1
X
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
IN UART MODE 2 OR MODE 3 AND SM2_0 = 1:
INTERRUPT IF REN_0=1, RB8_0=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2_0 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2_0 TO WAIT FOR NEXT ADDRESS.
SU01332
Figure 18. UART Multiprocessor Communication, Automatic Address Recognition
INPUT/OUTPUT PORT PIN CONFIGURATION
Each I/O port pin can be user–configured to one of four modes:
Quasi–Bidirectional (essentially the same as standard 80C51 family
I/O ports), Open–Drain, Push–Pull, and Off (High Impedance). After
Reset, the default configuration is Quasi–Bidirectional.
I/O port pin configurations are determined by the settings in port
configuration SFRs. There are two SFRs for each port, called
PnCFGA and PnCFGB, where “n” is the port number. One bit in
each of the two SFRs relates to the setting for the corresponding
port pin, allowing any combination of the four modes to be mixed on
any port pins. For instance, the mode of port 1 pin 3 (P1.3) is
controlled by setting bit 3 (P1CFGA[3] and P1CFGB[3]).
Table 13 shows the configuration register settings for the four port
pin modes. The DC electrical characteristics of each mode may be
found in Table 19.
Table 13. Port Configuration Register Settings
PnCFGB
PnCFGA
Port Pin Mode
0
0
Open–Drain
0
1
Quasi–Bidirectional
1
0
Off (High Impedance)
1
1
Push–Pull
Note: Mode changes may cause glitches to occur during transitions.
When modifying both registers, WRITE instructions should be
carried out consecutively.
EXTERNAL BUS
If off chip code is selected (through the use of the EA/ pin), initial
code fetches will be done within a full 20–bit address space. The
External PROGRAM/DATA bus provides 16 bit width in a 20–bit
ADDRESS space.
RESET
Refer to Figure 19 for a recommended Reset circuit example.
V
DD
R
C
RESET
XA
SOME TYPICAL VALUES FOR R AND C:
R = 100K, C = 1.0
μ
F
R = 1.0M, C = 0.1
μ
F
(ASSUMING THAT THE V
DD
RISE TIME IS 1ms OR LESS)
SU00702
Figure 19. Recommended Reset Circuit
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