參數(shù)資料
型號(hào)： X96012V14I
廠商： INTERSIL CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： Universal Sensor Conditioner with Dual Look Up Table Memory and DACs
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO14
封裝： PLASTIC, MO-153AC, TSSOP-14
文件頁(yè)數(shù)： 7/27頁(yè)
文件大?。?/td> 383K
代理商： X96012V14I
7
FN8216.0
March 10, 2005
A/D CONVERTER CHARACTERISTICS
(See pg. 4 for Standard Conditions)
.
Notes: 1.
“LSB” is defined as V(VRef)/255, “Full Scale” is defined as V(VRef).
Offset
ADC
: For an ideal converter, the first transition of its transfer curve occurs at
amount of deviation between the measured first transition point and the ideal point.
FSError
ADC
: For an ideal converter, the last transition of its transfer curve occurs at
amount of deviation between the measured last transition point and the ideal point,
after subtracting the Offset from the measured curve.
DNL
ADC
: DNL is defined as the difference between the ideal and the measured code transitions for successive A/D code outputs
expressed in LSBs. The measured transfer curve is adjusted for Offset and Fullscale errors before calculating DNL.
INL
ADC
: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is also
defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured trans-
fer curve is adjusted for Offset and Fullscale errors before calculating INL.
These parameters are periodically sampled and not 100% tested.
2.
above zero. Offset error is the
]
. Full Scale Error is the
3.
Symbol
ADCTIME
Parameter
Min
Typ
Max
9
Unit
ms
Test Conditions / Notes
Proportional to A/D converter
input voltage. This value is
maximum at full scale input
of A/D converter.
ADCfiltOff = “1”
VSense as an input,
ADCIN bit = “1”
VSense as an input,
ADCIN bit = “1”,
Frequency = 1 MHz
See note 3.
This is the A/D Converter
Dynamic Range. ADCIN bit = “1”
A/D converter conversion
time
RIN
ADC
VSense pin input
resistance
VSense pin input
capacitance
100
k
CIN
ADC
1
7
pF
VIN
ADC
VSense input signal range
0
V(VRef)
V
The ADC is monotonic
Offset
ADC
FSError
ADC
A/D converter offset error
A/D converter full scale
error
A/D Converter Differential
Nonlinearity
A/D converter Integral
Nonlinearity
Temperature step causing
one step increment of ADC
output
ADC output at 25°C
±1
±1
LSB
LSB
See notes 1 and 2
DNL
ADC
±0.5
LSB
INL
ADC
±1
LSB
TempStep
ADC
0.52
0.55
0.58
°C
See note 3
Out25
ADC
01110101
2
0.5
x V(VRef)
255
254.5
x V(VRef)
[
[
]
255
X96012
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