參數資料
型號: X96012V14I
廠商: INTERSIL CORP
元件分類: 模擬信號調理
英文描述: Universal Sensor Conditioner with Dual Look Up Table Memory and DACs
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO14
封裝: PLASTIC, MO-153AC, TSSOP-14
文件頁數: 26/27頁
文件大?。?/td> 383K
代理商: X96012V14I
26
FN8216.0
March 10, 2005
The Data Bytes are from the memory location indicated
by an internal pointer. This pointer initial value is deter-
mined by the Address Byte in the Read operation instruc-
tion, and increments by one during transmission of each
Data Byte. After reaching the memory location 10Fh the
pointer “rolls over” to 00h, and the device continues to
output data for each ACK received.
A Read operation internal pointer can start at any
memory location from 00h through FEh, when the
Address Byte is 00h through FEh respectively. But it
starts at location 100h if the Address Byte is FFh.
When reading any of the control registers 1, 2, 3, or 4,
the Data Bytes are always the content of the corre-
sponding nonvolatile cells, even if bit NV1234 is "0"
(See “Control and Status Register Format”).
Data Protection
There are four levels of data protection designed into
the X96012: 1- Any Write to the device first requires
setting of the WEL bit in Control 6 register; 2- The
Block Lock can prevent Writes to certain regions of
memory; 3- The Write Protection pin disables any writ-
ing to the X96012; 4- The proper clock count, data bit
sequence, and STOP condition is required in order to
start a nonvolatile write cycle, otherwise the X96012
ignores the Write operation.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (LOW),
any Write operations to the X96012 is disabled, except
the writing of the WEL bit.
Signals
from the
Master
Signals from
the Slave
Signal at
SDA
S
t
a
r
t
Slave
Address
with
R/W=0
Address
Byte
A
C
K
A
C
K
1
0
1
0
0
S
t
o
p
A
C
K
1
1
1
0
0
Slave
Address
with
R/W=1
A
C
K
S
t
a
r
t
Last Read
Data Byte
First Read
Data Byte
A
C
K
Figure 22. Read Sequence
X96012
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