參數(shù)資料
型號(hào)： X96012V14I
廠商： INTERSIL CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： Universal Sensor Conditioner with Dual Look Up Table Memory and DACs
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO14
封裝： PLASTIC, MO-153AC, TSSOP-14
文件頁數(shù)： 11/27頁
文件大?。?/td> 383K
代理商： X96012V14I
11
FN8216.0
March 10, 2005
PRINCIPLES OF OPERATION
CONTROL AND STATUS REGISTERS
The Control and Status Registers provide the user
with a mechanism for changing and reading the value
of various parameters of the X96012. The X96012
contains seven Control, one Status, and several
Reserved registers, each being one Byte wide (See
Figure 4). The Control registers 0 through 6 are
located at memory addresses 80h through 86h
respectively. The Status register is at memory address
87h, and the Reserved registers at memory address
88h through 8Fh.
All bits in Control register 6 always power-up to the
logic state “0”. All bits in Control registers 0 through 5
power-up to the logic state value kept in their corre-
sponding nonvolatile memory cells. The nonvolatile
bits of a register retain their stored values even when
the X96012 is powered down, then powered back up.
The nonvolatile bits in Control 0 through Control 5 reg-
isters are all preprogrammed to the logic state “0” at
the factory.
Bits indicated as “Reserved” are ignored when read,
and must be written as “0”, if any Write operation is
performed to their registers.
A detailed description of the function of each of the
Control and Status register bits follows:
Control Register 0
This register is accessed by performing a Read or
Write operation to address 80h of memory.
BL1, BL0: B
LOCK
L
OCK
PROTECTION
BITS
(N
ON
-
VOLATILE
)
These two bits are used to inhibit any write operation
to certain addresses within the memory array. The
protected region of memory is determined by the val-
ues of the two bits as shown in the table below:
If the user attempts to perform a write operation to a
protected region of memory, the operation is aborted
without changing any data in the array.
Notice that if the Write Protect (WP) input pin of the
X96012 is active (LOW), then any write operation to
the memory is inhibited, irrespective of the Block Lock
bit settings.
VRM: V
OLTAGE
R
EFERENCE
PIN
M
ODE
(N
ON
-
VOLATILE
)
The VRM bit configures the Voltage Reference pin
(VRef) as either an input or an output. When the VRM
bit is set to “0” (default), the voltage at pin VRef is an
output from the X96012’s internal voltage reference.
When the VRM bit is set to “1”, the voltage reference
for the VRef pin is external. See Figure 5.
ADCIN: A/D C
ONVERTER
I
NPUT
S
ELECT
(N
ON
-
VOLATILE
)
The ADCIN bit selects the input of the on-chip A/D
converter. When the ADCIN bit is set to “0” (default),
the output of the on-chip temperature sensor is the
input to the A/D converter. When the ADCIN bit is set
to “1”, the input to the A/D converter is the voltage at
the VSense pin. See Figure 7.
ADC
FILT
O
FF
: ADC F
ILTERING
C
ONTROL
(N
ON
-
VOLATILE
)
When this bit is“1”, the status register at 87h is
updated after every conversion of the ADC. When this
bit is “0” (default), the status register is updated after
four consecutive conversions with the same result, on
the 6 MSBs.
NV1234: C
ONTROL
REGISTERS
1, 2, 3,
AND
4
VOLA
-
TILITY
MODE
SELECTION
BIT
(N
ON
-
VOLATILE
)
When the NV1234 bit is set to “0” (default), bytes writ-
ten to Control registers 1, 2, 3, and 4 are stored in vol-
atile cells, and their content is lost when the X96012 is
powered down. When the NV1234 bit is set to “1”,
bytes written to Control registers 1, 2, 3, and 4 are
stored in both volatile and nonvolatile cells, and their
value doesn’t change when the X96012 is powered
down and powered back up. See “Writing to Control
Registers” on page 24.
I1DS: C
URRENT
G
ENERATOR
1 D
IRECTION
S
ELECT
B
IT
(N
ON
-
VOLATILE
)
The I1DS bit sets the polarity of Current Generator 1,
DAC1. When this bit is set to “0” (default), the Current
Generator 1 of the X96012 is configured as a Current
Source. Current Generator 1 is configured as a Cur-
rent Sink when the I1DS bit is set to “1”. See Figure 8.
B
B
Protected Addresses
(Size)
None (Default)
00h to 7Fh (128 bytes)
00h to 7Fh and 90h to
CFh (192 bytes)
00h to 7Fh and 90h to
10Fh (256 bytes)
Partition of array
locked
None (Default)
GPM
GPM, LUT1
0
0
1
0
1
0
1
1
GPM, LUT1, LUT2
X96012
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