參數(shù)資料
型號: X4C105
元件分類: CPU監(jiān)測
英文描述: RTC Module With CPU Supervisor
中文描述: 時(shí)鐘模塊CPU監(jiān)控
文件頁數(shù): 6/18頁
文件大?。?/td> 93K
代理商: X4C105
X4C105
6
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. Refer to figure 7 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
plus the subsequent ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte plus its
associated ACK is sent, then the device will reset itself
without performing the write. The contents of the array
will not be affected.
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1 < n < 16)
Figure 7. Page Write Operation
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