參數(shù)資料
型號: X4C105
元件分類: CPU監(jiān)測
英文描述: RTC Module With CPU Supervisor
中文描述: 時鐘模塊CPU監(jiān)控
文件頁數(shù): 1/18頁
文件大?。?/td> 93K
代理商: X4C105
ó
9900-3002.11 2/24/99 EP
Xicor, Inc. 1994, 1995, 1996 Patents Pending
1
Characteristics subject to change without notice
4K
NOVRAM/EEPROM
CPU Supervisor with NOVRAM and Output Ports
FEATURES
4kbit Serial EEPROM
—400kHz Serial Interface speed
—16-Byte Page Write Mode
One Nibble NOVRAM
—120ns NOVRAM access speed
—AUTOSTORE
—Direct/Bus access of NOVRAM bits
Four Output Ports
Operates at 3.3V +/- 10%
Low Voltage Reset when Vcc < 3V.
—Output signal shows low voltage condition
—Activates NOVRAM AUTOSTORE.
—Internal Block on EEPROM operation
Max EEPROM/NOVRAM Nonvolatile Write Cycle:
5ms
High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 years
20-L TSSOP package
DESCRIPTION
The low voltage X4C105 combines several functions into
one device. The first is a 2-wire, 4Kbit serial EEPROM
memory with write protection. A Write Protect (WP) pin
provides hardware protection for the upper half of this
memory against inadvertent writes.
A one nibble NOVRAM is provided and occupies a single
location. This allows access of 4 bits in a single 150ns
cycle. This is useful for tracking system operation or
process status. The NOVRAM memory is completely
isolated from the serial memory section.
A low voltage detect circuit activates a RESET pin when
Vcc drops below 3V. This signal also blocks new read or
write operations and initiates a NOVRAM AUTOSTORE.
The AUTOSTORE operation is powered by an external
capacitor to ensure that the value in the NOVRAM is
always maintained in the event of a power failure.
The four NOVRAM bits also appear on four seperate
output pins to allow continuous control of external
circuitry, such as ASICs.
Xicor EEPROMs are designed and tested for
applications requiring extended endurance. Inherent data
retention is greater than 100 years.
DEVICE BLOCK DIAGRAM
Command
Decode
and
Control
Logic
HV Generation
Timing and Control
EEPROM
Array
X
Y Decoder
Data Register
Write Control Logic
WP
SCL
SDA
S1
S2
D0
D1
D2
D3
CE
OE
WE
I/O
Buffers
Control
Logic and
Timing
Static RAM
Memory
4 bits
EEPROM
Memory
Vcc
Vss
RESET
Voltage
Monitor
Supply
Power On Reset
Low Voltage Detect
CAP
O0
O1
O2
O3
Output-
Buffers
and
Latches
X4C105
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