參數(shù)資料
型號(hào): X4C105
元件分類: CPU監(jiān)測(cè)
英文描述: RTC Module With CPU Supervisor
中文描述: 時(shí)鐘模塊CPU監(jiān)控
文件頁(yè)數(shù): 2/18頁(yè)
文件大?。?/td> 93K
代理商: X4C105
X4C105
2
Package/Pinouts
Pin Names:
VSS
SDA
VCC
SCL
WP
S1, S2
CAP
D0-D3
RESET
CE
OE
WE
O0-O3
Ground
Serial Data
Power
Serial Clock
Write Protect
Device Select Inputs
External AUTOSTORE Capacitor
NOVRAM I/Os
Low Voltage Detect Output
NOVRAM Chip Enable
NOVRAM Read Signal
NOVRAM Write signal
NOVRAM Outputs
DEVICE DESCRIPTION
Serial Memory Section
The device contains a 4K-bit EEPROM memory array
with an internal address counter that allows it to be read
sequentially, through its entire address space after
receiving only 1 full address. The serial interface includes
a current address read that requires no input address,
but allows reading of the entire array starting from the
address plus one of the last read or write. The address
counter is also used for the write operation where the
user may enter up to a page of data (16 bytes) after
supplying only 1 full address.
A WP pin provides Hardware Write Protection. The WP
pin active (HIGH) prevents writes to the top half of the
memory.
This section is a 4K-bit version of an industry standard
24C03 device.
NOVRAM Section
The X4C105 also contains a single nibble of NOVRAM,
with parallel access. This memory is completely isolated
from the serial memory section. The NOVRAM is
intended to connect to the system memory bus and uses
standard CE, OE, and WE pins to control access.
A NOVRAM (or nonvolatile RAM) consists of an SRAM
part and an EEPROM part. The SRAM is saved to
EEPROM only when power fails and the EEPROM is
recalled to SRAM only on power up.
Output Ports
The X4C105 has four output only ports. These are active
whenever power is applied to the device. The state of the
output pin reflects the value in the respective SRAM bit.
As such, these port pins provide a nonvolatile state. The
conditions on the pins are restored when power is re-
applied to the device. This can be valuable as a DIP
Switch replacment for controlling the conditions of an
ASIC or other system logic.
Low Voltage Detection
When the internal low voltage detect circuitry senses that
Vcc is low, several things happen:
— The RESET pin goes active.
— The contents of the SRAM are automatically saved
to the “shadow” EEPROM.
— Internal circuitry switches to provide power for the
autostore operation from the CAP pin so the store
operation can complete even in the event of a cata-
strophic power failure. To insure this, it is recom-
mended that a 47uF capacitor be used on the CAP
pin. The capacitor is continuously charged during
normal operation to provide the necessary charge to
complete the store operation. Other internal circuits
are turned off to minimize current consumption dur-
ing the store operations.
— Communication to the device is interrupted and any
command is aborted. If a serial nonvolatile store is in
progress when power fails, the operation is com-
pleted and is followed by a NOVRAM AUTOSTORE
cycle.
Capacitor Backup Circuit
The diagram in Figure1 shows a representation of the
Capacitor backup circuit.
S1
O0
V
CC
WP
SDA
SCL
CAP
S2
RESET
CE
WE
OE
D0
D3
D2
D1
V
SS
O1
O2
O3
3
2
4
1
18
19
17
20
7
6
8
5
14
15
13
16
9
10
12
11
20L TSSOP
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