參數(shù)資料
型號(hào): X4C105
元件分類: CPU監(jiān)測(cè)
英文描述: RTC Module With CPU Supervisor
中文描述: 時(shí)鐘模塊CPU監(jiān)控
文件頁數(shù): 3/18頁
文件大?。?/td> 93K
代理商: X4C105
X4C105
3
S
ERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is called
the master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive
operations. Therefore, the devices in this family operate
as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved
for indicating start and stop conditions. See figure 2.
Serial Start Condition
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL lines
for the start condition and will not respond to any
command until this condition has been met. See figure 3.
Start
NOVRAM
AUTOSTORE
To internal
voltage supply
HIGH when
V
CC
> V
LOW when
<V
TRIP
TRIP
V
CC
-0.2V
V
TRIP
V
CC
CAP
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 2. Valid Data Changes on the SDA Bus
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