參數(shù)資料
型號: WM8191
廠商: Wolfson Microelectronics
英文描述: TVS BI-DIR 6.0V 400W SMA
中文描述: 14位6MSPS獨聯(lián)體/防治荒漠化公約模擬前端/數(shù)字轉(zhuǎn)換器
文件頁數(shù): 2/27頁
文件大?。?/td> 355K
代理商: WM8191
WM8191
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 3.1 April 2001
2
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
XWM8191CFT
0 to 70
°
C
48-pin TQFP
1mm thick body
V
A
A
A
A
V
O
O
O
D
N
N
37
47 46 45 44 43 42 41 40 39 38
48
D
D
O
N
N
O
O
V
S
S
R
M
VRX
AGND3
RINP
AGND4
DVDD1
OEB
SEN/STB
GINP
AGND2
BINP
AGND1
VRLC/VBIAS
DGND4
DVDD3
DGND3
OP[6]
OP[7]
OP[8]
OP[9]
OP[10]
DGND2
OP[3]
OP[4]
OP[5]
25
31
30
29
28
27
26
36
35
34
33
32
1
2
9
10
8
7
6
5
4
3
12
11
24
23
16 17 18 19 20 21 22
13 14 15
PIN DESCRIPTION
PIN
1
NAME
VRX
TYPE
DESCRIPTION
Input return bias voltage.
This pin must be decoupled to AGND via a capacitor.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be decoupled to AGND via a capacitor.
VRLC can be externally driven if programmed Hi-Z.
Analogue ground (0V).
Blue channel input video.
Analogue ground (0V).
Green channel input video.
Analogue ground (0V).
Red channel input video.
Analogue ground (0V).
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
Output Hi-Z control, all digital outputs disabled when OEB = 1.
Serial interface: enable pulse, active high
Latched on NRESET rising edge: if Low then device control is via serial interface,
if high then device control is via parallel interface.
Serial interface: serial input data signal
Analogue output
2
VRLC/VBIAS
Analogue I/O
3
4
5
6
7
8
9
10
AGND1
BINP
AGND2
GINP
AGND3
RINP
AGND4
DVDD1
Supply
Analogue input
Supply
Analogue input
Supply
Analogue input
Supply
Supply
11
12
OEB
Digital input
Digital input
Parallel interface: strobe, active low
SEN/STB
13
SDI/DNA
Digital input
Parallel interface:
High = data, Low = address
Parallel interface:
High: OP[13:6] is output bus.
Low: OP[13:6] is input bus (Hi-Z).
14
SCK/RNW
Digital input
Serial interface: serial clock signal
15
16
VSMP
RLC/ACYC
Digital input
Digital input
Video sample synchronisation pulse.
RLC (active high) selects reset level
clamp on a pixel-by-pixel basis
tie high
if used on every pixel.
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
Digital ground (0V).
No connection.
No connection.
ACYC autocycles between R, G, B
inputs when in Line-by-Line mode.
17
MCLK
Digital input
18
19
20
DGND1
NC
NC
Supply
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